Abstract: A method includes the steps of obtaining a frame from an image sensor, the frame comprising a number of pixel values, detecting a change in a first subset of the pixel values, detecting a change in the second subset of the pixel values near the first subset of the pixel values, and determining an occupancy state based on a relationship between the change in the first subset of the pixel values and the second subset of the pixel values. The occupancy state may be determined to be occupied when the change in the first subset of the pixel values is in a first direction and the change in the second subset of the pixel values is in a second direction opposite the first direction.

Abstract: A method includes the steps of obtaining a frame from an image sensor, the frame comprising a number of pixel values, detecting a change in a first subset of the pixel values, detecting a change in the second subset of the pixel values near the first subset of the pixel values, and determining an occupancy state based on a relationship between the change in the first subset of the pixel values and the second subset of the pixel values. The occupancy state may be determined to be occupied when the change in the first subset of the pixel values is in a first direction and the change in the second subset of the pixel values is in a second direction opposite the first direction.

Abstract: A method includes the steps of obtaining a frame from an image sensor, the frame comprising a number of pixel values, detecting a change in a first subset of the pixel values, detecting a change in the second subset of the pixel values near the first subset of the pixel values, and determining an occupancy state based on a relationship between the change in the first subset of the pixel values and the second subset of the pixel values. The occupancy state may be determined to be occupied when the change in the first subset of the pixel values is in a first direction and the change in the second subset of the pixel values is in a second direction opposite the first direction.

Abstract: Simplified LED chip architectures or chip builds are disclosed that can result in simpler manufacturing processes using fewer steps. The LED structure can have fewer layers than conventional LED chips with the layers arranged in different ways for efficient fabrication and operation. The LED chips can comprise an active LED structure. A dielectric reflective layer is included adjacent to one of the oppositely doped layers. A metal reflective layer is on the dielectric reflective layer, wherein the dielectric and metal reflective layers extend beyond the edge of said active region. By extending the dielectric layer, the LED chips can emit with more efficiency by reflecting more LED light to emit in the desired direction. By extending the metal reflective layer beyond the edge of the active region, the metal reflective layer can serve as a current spreading layer and barrier, in addition to reflecting LED light to emit in the desired direction.

Abstract: A method includes the steps of obtaining a frame from an image sensor, the frame comprising a number of pixel values, detecting a change in a first subset of the pixel values, detecting a change in the second subset of the pixel values near the first subset of the pixel values, and determining an occupancy state based on a relationship between the change in the first subset of the pixel values and the second subset of the pixel values. The occupancy state may be determined to be occupied when the change in the first subset of the pixel values is in a first direction and the change in the second subset of the pixel values is in a second direction opposite the first direction.

Abstract: A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle.

Abstract: Simplified LED chip architectures or chip builds are disclosed that can result in simpler manufacturing processes using fewer steps. The LED structure can have fewer layers than conventional LED chips with the layers arranged in different ways for efficient fabrication and operation. The LED chips can comprise an active LED structure. A dielectric reflective layer is included adjacent to one of the oppositely doped layers. A metal reflective layer is on the dielectric reflective layer, wherein the dielectric and metal reflective layers extend beyond the edge of said active region. By extending the dielectric layer, the LED chips can emit with more efficiency by reflecting more LED light to emit in the desired direction. By extending the metal reflective layer beyond the edge of the active region, the metal reflective layer can serve as a current spreading layer and barrier, in addition to reflecting LED light to emit in the desired direction.

Abstract: A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle.

Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.

Abstract: Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications. A guard ring is a floating electrode formed of electrically conducting material above a semiconductor material layer. A portion of an insulating layer is between at least a portion of the guard ring and the semiconductor material layer. A guard ring may be located, for example, on a transistor between a gate and a drain electrode. A semiconductor device may have one or more guard rings.

Abstract: A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle.

Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

Abstract: A III-N semiconductor device can include an electrode-defining layer having a thickness on a surface of a III-N material structure. The electrode-defining layer has a recess with a sidewall, the sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, the first width being larger than the second width. An electrode is in the recess, the electrode including an extending portion over the sidewall of the recess. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The sidewall forms an effective angle of about 40 degrees or less relative to the surface of the III-N material structure.

Abstract: Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications. A guard ring is a floating electrode formed of electrically conducting material above a semiconductor material layer. A portion of an insulating layer is between at least a portion of the guard ring and the semiconductor material layer. A guard ring may be located, for example, on a transistor between a gate and a drain electrode. A semiconductor device may have one or more guard rings.

Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.

Abstract: A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.

Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

Abstract: Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications. A guard ring is a floating electrode formed of electrically conducting material above a semiconductor material layer. A portion of an insulating layer is between at least a portion of the guard ring and the semiconductor material layer. A guard ring may be located, for example, on a transistor between a gate and a drain electrode. A semiconductor device may have one or more guard rings.

Abstract: A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.

Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.