Patents by Inventor Yuvaraj Dora
Yuvaraj Dora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8860495Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.Type: GrantFiled: October 31, 2013Date of Patent: October 14, 2014Assignee: Transphorm Inc.Inventors: Rakesh K. Lal, Robert Coffie, Yifeng Wu, Primit Parikh, Yuvaraj Dora, Umesh Mishra, Srabanti Chowdhury, Nicholas Fichtenbaum
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Publication number: 20140273422Abstract: A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.Type: ApplicationFiled: May 28, 2014Publication date: September 18, 2014Applicant: Transphorm, Inc.Inventor: Yuvaraj Dora
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Publication number: 20140231823Abstract: A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle.Type: ApplicationFiled: February 13, 2014Publication date: August 21, 2014Applicant: Transphorm Inc.Inventors: Srabanti Chowdhury, Umesh Mishra, Yuvaraj Dora
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Publication number: 20140197421Abstract: A III-N semiconductor device can include an electrode-defining layer having a thickness on a surface of a III-N material structure. The electrode-defining layer has a recess with a sidewall, the sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, the first width being larger than the second width. An electrode is in the recess, the electrode including an extending portion over the sidewall of the recess. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The sidewall forms an effective angle of about 40 degrees or less relative to the surface of the III-N material structure.Type: ApplicationFiled: March 14, 2014Publication date: July 17, 2014Applicant: Transphorm Inc.Inventors: Yuvaraj Dora, Yifeng Wu
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Patent number: 8772842Abstract: A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.Type: GrantFiled: March 4, 2011Date of Patent: July 8, 2014Assignee: Transphorm, Inc.Inventor: Yuvaraj Dora
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Patent number: 8716141Abstract: A III-N semiconductor device can include an electrode-defining layer having a thickness on a surface of a III-N material structure. The electrode-defining layer has a recess with a sidewall, the sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, the first width being larger than the second width. An electrode is in the recess, the electrode including an extending portion over the sidewall of the recess. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The sidewall forms an effective angle of about 40 degrees or less relative to the surface of the III-N material structure.Type: GrantFiled: March 4, 2011Date of Patent: May 6, 2014Assignee: Transphorm Inc.Inventors: Yuvaraj Dora, Yifeng Wu
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Publication number: 20140099757Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.Type: ApplicationFiled: December 11, 2013Publication date: April 10, 2014Applicant: Transphorm Inc.Inventors: Primit Parikh, Yuvaraj Dora, Yifeng Wu, Umesh Mishra, Nicholas Fichtenbaum, Rakesh K. Lal
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Publication number: 20140094010Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.Type: ApplicationFiled: October 31, 2013Publication date: April 3, 2014Applicant: Transphorm Inc.Inventors: Rakesh L. Lal, Robert Coffie, Yifeng Wu, Primit Parikh, Yuvaraj Dora, Umesh Mishra, Srabanti Chowdhury, Nicholas Fichtenbaum
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Patent number: 8643062Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.Type: GrantFiled: February 2, 2011Date of Patent: February 4, 2014Assignee: Transphorm Inc.Inventors: Primit Parikh, Yuvaraj Dora, Yifeng Wu, Umesh Mishra, Nicholas Fichtenbaum, Rakesh K. Lal
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Patent number: 8598937Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.Type: GrantFiled: October 7, 2011Date of Patent: December 3, 2013Assignee: Transphorm Inc.Inventors: Rakesh K. Lal, Robert Coffie, Yifeng Wu, Primit Parikh, Yuvaraj Dora, Umesh Mishra, Srabanti Chowdhury, Nicholas Fichtenbaum
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Publication number: 20130088280Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.Type: ApplicationFiled: October 7, 2011Publication date: April 11, 2013Applicant: TRANSPHORM INC.Inventors: Rakesh K. Lal, Robert Coffie, Yifeng Wu, Primit Parikh, Yuvaraj Dora, Umesh Mishra, Srabanti Chowdhury, Nicholas Fichtenbaum
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Publication number: 20130056744Abstract: Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications. A guard ring is a floating electrode formed of electrically conducting material above a semiconductor material layer. A portion of an insulating layer is between at least a portion of the guard ring and the semiconductor material layer. A guard ring may be located, for example, on a transistor between a gate and a drain electrode. A semiconductor device may have one or more guard rings.Type: ApplicationFiled: September 6, 2011Publication date: March 7, 2013Applicant: TRANSPHORM INC.Inventors: Umesh Mishra, Srabanti Chowdhury, Yuvaraj Dora
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Publication number: 20120223319Abstract: A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.Type: ApplicationFiled: March 4, 2011Publication date: September 6, 2012Applicant: TRANSPHORM INC.Inventor: Yuvaraj Dora
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Publication number: 20120223320Abstract: A III-N semiconductor device can include an electrode-defining layer having a thickness on a surface of a III-N material structure. The electrode-defining layer has a recess with a sidewall, the sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, the first width being larger than the second width. An electrode is in the recess, the electrode including an extending portion over the sidewall of the recess. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The sidewall forms an effective angle of about 40 degrees or less relative to the surface of the III-N material structure.Type: ApplicationFiled: March 4, 2011Publication date: September 6, 2012Applicant: TRANSPHORM INC.Inventor: Yuvaraj Dora
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Publication number: 20120193677Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.Type: ApplicationFiled: February 2, 2011Publication date: August 2, 2012Applicant: TRANSPHORM INC.Inventors: Primit Parikh, Yuvaraj Dora, Yifeng Wu, Umesh Mishra, Nicholas Fichtenbaum
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Publication number: 20080308813Abstract: High breakdown enhancement mode gallium nitride (GaN) based high electron mobility transistors (HEMTs) with integrated slant field plates. These HEMTs have an epilayer structure comprised of AlGaN/GaN buffer. Before the formation of the gate electrode, a passivation layer is deposited, and then the opening for the gate is patterned. The passivation layer below the gate is etched using an etch condition that creates a slanted sidewalls. Then, the charge below the channel is removed either by Fluorine-based plasma treatment and/or by a recess etch. The gate metal is deposited with an angled rotation to form a gate structure with an inherent field plate with rounded edges.Type: ApplicationFiled: August 20, 2007Publication date: December 18, 2008Inventors: Chang Soo Suh, Yuvaraj Dora, Umesh K. Mishra