Patents by Inventor Yu-Wei Kuo

Yu-Wei Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11854873
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Lun Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
  • Publication number: 20230377963
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Lun KE, Yu-Wei KUO, Yi-Wei CHIU, Hung Jui CHANG
  • Patent number: 11824288
    Abstract: A cable connection device is provided. The cable connection device includes a casing, a connection component, a power cable and a circuit board. The casing includes a first accommodation space, a second accommodation space and a channel. The channel is in communication between the first accommodation space and the second accommodation space. The connection component is penetrated through the channel and includes a clamping part disposed in the first accommodation space and a first conductive part disposed in the second accommodation space. Portion of the power cable is disposed in the first accommodation space. The clamping part clamps the power cable and partially pierces the insulating sleeve, so that the clamping part is connected with the wire core. The circuit board is disposed in the second accommodation space and comprises second conductive part. The second conductive part is contacted with the first conductive part.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: November 21, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Hung-Sheng Hsieh, Yu-Wei Kuo
  • Patent number: 11569125
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
  • Patent number: 11557694
    Abstract: A light emitting device includes: a plurality of light emitting stacked layers, including a first surface and a second surface, wherein the second surface is electrically opposite to the first surface; a mesa structure; a current blocking layer disposed on the first surface, including a sidewall; and a transparent conductive layer disposed on the first surface; and a first pad electrode, disposed on the transparent conductive layer and on the first surface; wherein a retract distance of the transparent conductive layer with respect to an edge of the mesa structure is less than 3 ?m; and wherein a retract distance of the transparent conductive layer with respect to an edge of the sidewall of the current blocking layer is less than 3 ?m.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: January 17, 2023
    Assignee: EPISTAR CORPORATION
    Inventors: Chien Cheng Huang, Kuo-Wei Yen, Yu-Wei Kuo, Yao-Wei Yang, Pei-Hsiang Tseng
  • Publication number: 20220416454
    Abstract: A cable connection device is provided. The cable connection device includes a casing, a connection component, a power cable and a circuit board. The casing includes a first accommodation space, a second accommodation space and a channel. The channel is in communication between the first accommodation space and the second accommodation space. The connection component is penetrated through the channel and includes a clamping part disposed in the first accommodation space and a first conductive part disposed in the second accommodation space. Portion of the power cable is disposed in the first accommodation space. The clamping part clamps the power cable and partially pierces the insulating sleeve, so that the clamping part is connected with the wire core. The circuit board is disposed in the second accommodation space and comprises second conductive part. The second conductive part is contacted with the first conductive part.
    Type: Application
    Filed: October 13, 2021
    Publication date: December 29, 2022
    Inventors: Hung-Sheng Hsieh, Yu-Wei Kuo
  • Publication number: 20220093457
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
  • Patent number: 11195750
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: December 7, 2021
    Assignee: Tawiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
  • Publication number: 20210249561
    Abstract: A light emitting device includes: a plurality of light emitting stacked layers, including a first surface and a second surface, wherein the second surface is electrically opposite to the first surface; a mesa structure; a current blocking layer disposed on the first surface, including a sidewall; and a transparent conductive layer disposed on the first surface; and a first pad electrode, disposed on the transparent conductive layer and on the first surface; wherein a retract distance of the transparent conductive layer with respect to an edge of the mesa structure is less than 3 ?m; and wherein a retract distance of the transparent conductive layer with respect to an edge of the sidewall of the current blocking layer is less than 3 ?m.
    Type: Application
    Filed: February 19, 2021
    Publication date: August 12, 2021
    Inventors: Chien Cheng HUANG, Kuo-Wei YEN, Yu-Wei KUO, Yao-Wei YANG, Pei-Hsiang TSENG
  • Patent number: 11075087
    Abstract: A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chi Lin, Chin-Hsing Lin, Hung Jui Chang, Yi-Wei Chiu, Yu-Wei Kuo, Yu Lun Ke
  • Patent number: 10930818
    Abstract: A light emitting device includes: a plurality of light emitting stacked layers, including a first surface and a second surface, wherein the second surface is electrically opposite to the first surface; a mesa structure; and a current blocking (CB) layer disposed on the first surface; a transparent conductive layer disposed on or above the first surface; and a first pad electrode, disposed on the transparent conductive layer and on the first surface; wherein a sidewall of the CB layer comprises a first surface section and a second surface section having different slopes.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: February 23, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Chien Cheng Huang, Kuo-Wei Yen, Yu-Wei Kuo, Yao-Wei Yang, Pei-Hsiang Tseng
  • Publication number: 20200328113
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen Ke, Yi-Wei CHIU, Hung Jui CHANG, Yu-Wei KUO
  • Patent number: 10707123
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
  • Publication number: 20200058513
    Abstract: A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 20, 2020
    Inventors: Yu-Chi Lin, Chin-Hsing Lin, Hung Jui Chang, Yi-Wei Chiu, Yu-Wei Kuo, Yu Lun Ke
  • Publication number: 20200043740
    Abstract: A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.
    Type: Application
    Filed: October 7, 2019
    Publication date: February 6, 2020
    Inventors: Yu-Chi Lin, Chin-Hsing Lin, Hung Jui Chang, Yi-Wei Chiu, Yu-Wei Kuo, Yu Lun Ke
  • Patent number: 10504738
    Abstract: A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chi Lin, Chin-Hsing Lin, Hung Jui Chang, Yi-Wei Chiu, Yu-Wei Kuo, Yu-Lun Ke
  • Publication number: 20190333784
    Abstract: A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: Yu-Chi Lin, Chin-Hsing Lin, Hung Jui Chang, Yi-Wei Chiu, Yu-Wei Kuo, Yu-Lun Ke
  • Publication number: 20190096754
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Application
    Filed: November 28, 2018
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen KE, Yi-Wei CHIU, Hung Jui CHANG, Yu-Wei KUO
  • Publication number: 20180315888
    Abstract: A light emitting device includes: a plurality of light emitting stacked layers, including a first surface and a second surface, wherein the second surface is electrically opposite to the first surface; a mesa structure; and a current blocking (CB) layer disposed on the first surface; a transparent conductive layer disposed on or above the first surface; and a first pad electrode, disposed on the transparent conductive layer and on the first surface; wherein a sidewall of the CB layer comprises a first surface section and a second surface section having different slopes.
    Type: Application
    Filed: July 6, 2018
    Publication date: November 1, 2018
    Inventors: CHIEN CHENG HUANG, KUO-WEI YEN, YU-WEI KUO, YAO-WEI YANG, PEI-HSIANG TSENG
  • Publication number: 20180315648
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Application
    Filed: October 5, 2017
    Publication date: November 1, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen KE, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo