Patents by Inventor Yu-Wei Kuo
Yu-Wei Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11854873Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: GrantFiled: December 6, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Lun Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
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Publication number: 20230377963Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Lun KE, Yu-Wei KUO, Yi-Wei CHIU, Hung Jui CHANG
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Patent number: 11824288Abstract: A cable connection device is provided. The cable connection device includes a casing, a connection component, a power cable and a circuit board. The casing includes a first accommodation space, a second accommodation space and a channel. The channel is in communication between the first accommodation space and the second accommodation space. The connection component is penetrated through the channel and includes a clamping part disposed in the first accommodation space and a first conductive part disposed in the second accommodation space. Portion of the power cable is disposed in the first accommodation space. The clamping part clamps the power cable and partially pierces the insulating sleeve, so that the clamping part is connected with the wire core. The circuit board is disposed in the second accommodation space and comprises second conductive part. The second conductive part is contacted with the first conductive part.Type: GrantFiled: October 13, 2021Date of Patent: November 21, 2023Assignee: DELTA ELECTRONICS, INC.Inventors: Hung-Sheng Hsieh, Yu-Wei Kuo
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Patent number: 11569125Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: GrantFiled: June 25, 2020Date of Patent: January 31, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
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Patent number: 11557694Abstract: A light emitting device includes: a plurality of light emitting stacked layers, including a first surface and a second surface, wherein the second surface is electrically opposite to the first surface; a mesa structure; a current blocking layer disposed on the first surface, including a sidewall; and a transparent conductive layer disposed on the first surface; and a first pad electrode, disposed on the transparent conductive layer and on the first surface; wherein a retract distance of the transparent conductive layer with respect to an edge of the mesa structure is less than 3 ?m; and wherein a retract distance of the transparent conductive layer with respect to an edge of the sidewall of the current blocking layer is less than 3 ?m.Type: GrantFiled: February 19, 2021Date of Patent: January 17, 2023Assignee: EPISTAR CORPORATIONInventors: Chien Cheng Huang, Kuo-Wei Yen, Yu-Wei Kuo, Yao-Wei Yang, Pei-Hsiang Tseng
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Publication number: 20220416454Abstract: A cable connection device is provided. The cable connection device includes a casing, a connection component, a power cable and a circuit board. The casing includes a first accommodation space, a second accommodation space and a channel. The channel is in communication between the first accommodation space and the second accommodation space. The connection component is penetrated through the channel and includes a clamping part disposed in the first accommodation space and a first conductive part disposed in the second accommodation space. Portion of the power cable is disposed in the first accommodation space. The clamping part clamps the power cable and partially pierces the insulating sleeve, so that the clamping part is connected with the wire core. The circuit board is disposed in the second accommodation space and comprises second conductive part. The second conductive part is contacted with the first conductive part.Type: ApplicationFiled: October 13, 2021Publication date: December 29, 2022Inventors: Hung-Sheng Hsieh, Yu-Wei Kuo
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Publication number: 20220093457Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
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Patent number: 11195750Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: GrantFiled: November 28, 2018Date of Patent: December 7, 2021Assignee: Tawiwan Semiconductor Manufacturing Co., Ltd.Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
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Publication number: 20210249561Abstract: A light emitting device includes: a plurality of light emitting stacked layers, including a first surface and a second surface, wherein the second surface is electrically opposite to the first surface; a mesa structure; a current blocking layer disposed on the first surface, including a sidewall; and a transparent conductive layer disposed on the first surface; and a first pad electrode, disposed on the transparent conductive layer and on the first surface; wherein a retract distance of the transparent conductive layer with respect to an edge of the mesa structure is less than 3 ?m; and wherein a retract distance of the transparent conductive layer with respect to an edge of the sidewall of the current blocking layer is less than 3 ?m.Type: ApplicationFiled: February 19, 2021Publication date: August 12, 2021Inventors: Chien Cheng HUANG, Kuo-Wei YEN, Yu-Wei KUO, Yao-Wei YANG, Pei-Hsiang TSENG
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Patent number: 11075087Abstract: A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.Type: GrantFiled: October 25, 2019Date of Patent: July 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chi Lin, Chin-Hsing Lin, Hung Jui Chang, Yi-Wei Chiu, Yu-Wei Kuo, Yu Lun Ke
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Patent number: 10930818Abstract: A light emitting device includes: a plurality of light emitting stacked layers, including a first surface and a second surface, wherein the second surface is electrically opposite to the first surface; a mesa structure; and a current blocking (CB) layer disposed on the first surface; a transparent conductive layer disposed on or above the first surface; and a first pad electrode, disposed on the transparent conductive layer and on the first surface; wherein a sidewall of the CB layer comprises a first surface section and a second surface section having different slopes.Type: GrantFiled: July 6, 2018Date of Patent: February 23, 2021Assignee: EPISTAR CORPORATIONInventors: Chien Cheng Huang, Kuo-Wei Yen, Yu-Wei Kuo, Yao-Wei Yang, Pei-Hsiang Tseng
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Publication number: 20200328113Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: ApplicationFiled: June 25, 2020Publication date: October 15, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Allen Ke, Yi-Wei CHIU, Hung Jui CHANG, Yu-Wei KUO
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Patent number: 10707123Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: GrantFiled: October 5, 2017Date of Patent: July 7, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
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Publication number: 20200058513Abstract: A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.Type: ApplicationFiled: October 25, 2019Publication date: February 20, 2020Inventors: Yu-Chi Lin, Chin-Hsing Lin, Hung Jui Chang, Yi-Wei Chiu, Yu-Wei Kuo, Yu Lun Ke
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Publication number: 20200043740Abstract: A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.Type: ApplicationFiled: October 7, 2019Publication date: February 6, 2020Inventors: Yu-Chi Lin, Chin-Hsing Lin, Hung Jui Chang, Yi-Wei Chiu, Yu-Wei Kuo, Yu Lun Ke
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Patent number: 10504738Abstract: A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.Type: GrantFiled: April 30, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chi Lin, Chin-Hsing Lin, Hung Jui Chang, Yi-Wei Chiu, Yu-Wei Kuo, Yu-Lun Ke
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Publication number: 20190333784Abstract: A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.Type: ApplicationFiled: April 30, 2018Publication date: October 31, 2019Inventors: Yu-Chi Lin, Chin-Hsing Lin, Hung Jui Chang, Yi-Wei Chiu, Yu-Wei Kuo, Yu-Lun Ke
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Publication number: 20190096754Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: ApplicationFiled: November 28, 2018Publication date: March 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Allen KE, Yi-Wei CHIU, Hung Jui CHANG, Yu-Wei KUO
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Publication number: 20180315888Abstract: A light emitting device includes: a plurality of light emitting stacked layers, including a first surface and a second surface, wherein the second surface is electrically opposite to the first surface; a mesa structure; and a current blocking (CB) layer disposed on the first surface; a transparent conductive layer disposed on or above the first surface; and a first pad electrode, disposed on the transparent conductive layer and on the first surface; wherein a sidewall of the CB layer comprises a first surface section and a second surface section having different slopes.Type: ApplicationFiled: July 6, 2018Publication date: November 1, 2018Inventors: CHIEN CHENG HUANG, KUO-WEI YEN, YU-WEI KUO, YAO-WEI YANG, PEI-HSIANG TSENG
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Publication number: 20180315648Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: ApplicationFiled: October 5, 2017Publication date: November 1, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Allen KE, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo