Patents by Inventor Yu-Wei Kuo
Yu-Wei Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984323Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.Type: GrantFiled: July 12, 2021Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
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Publication number: 20240154447Abstract: A power system including a first battery pack, a second battery pack, and a power management circuit is disclosed. The first battery pack has a first end and a second end, and has a first battery capacity. The second battery pack has a third end and a fourth end. The third end is coupled to the second end of the first battery pack and provides a low battery voltage. The fourth end is grounded, the second battery pack has a second battery capacity, and the second battery capacity is greater than the first battery capacity. The power management circuit is coupled to the second battery pack to receive the low battery voltage, and provides a component operating voltage to an electronic components based on the low battery voltage.Type: ApplicationFiled: August 29, 2023Publication date: May 9, 2024Applicant: PEGATRON CORPORATIONInventors: Yi-Hsuan Lee, Liang-Cheng Kuo, Chun-Wei Ko, Ya Ju Cheng, Chih Wei Huang, Ywh Woei Yeh, Yu Cheng Lin, Yen Ting Wang
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Patent number: 11978712Abstract: Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.Type: GrantFiled: November 16, 2020Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Wei Kuo, Hsiao-Tsung Yen, Min-Chie Jeng, Yu-Ling Lin
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Patent number: 11969447Abstract: A composition for promoting defecation includes a cell culture of at least one lactic acid bacterial strain which is substantially free of cells. The least one lactic acid bacterial strain is selected from the group consisting of Lactobacillus salivarius subsp. salicinius AP-32, Bifidobacterium animalis subsp. lactis CP-9, and Lactobacillus acidophilus TYCA06, which are respectively deposited at the Bioresource Collection and Research Center (BCRC) under accession numbers BCRC 910437, BCRC 910645 and BCRC 910813. Also disclosed is a method for promoting defecation, including administering to a subject in need thereof an effective amount of the composition.Type: GrantFiled: March 17, 2021Date of Patent: April 30, 2024Assignee: GLAC BIOTECH CO., LTD.Inventors: Hsieh-Hsun Ho, Ching-Wei Chen, Yi-Wei Kuo, Yu-Fen Huang, Cheng-Chi Lin
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Publication number: 20240133421Abstract: An electronic device includes a monitor stand, a hinge mechanism, and an operation element. The hinge mechanism includes a back plate, a speed reduction assembly, and a friction assembly. The back plate is fixed to the monitor stand. The speed reduction assembly includes an input plate and a speed reduction member. The speed reduction member is arranged on the input plate. The friction assembly is arranged between the back plate and the input plate. The operation element is connected to the speed reduction member. A rotation center of the operation element coincides with an axis of the back plate and the speed reduction member are coaxially arranged.Type: ApplicationFiled: January 17, 2023Publication date: April 25, 2024Inventors: Chih-Wei KUO, Yu-Chun HUNG, Che-Yen CHOU, Chen-Wei TSAI, Hsiang-Wen HUANG
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Patent number: 11961810Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.Type: GrantFiled: June 21, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
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Patent number: 11948938Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.Type: GrantFiled: July 18, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
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Patent number: 11943935Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.Type: GrantFiled: September 26, 2022Date of Patent: March 26, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
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Publication number: 20240097067Abstract: A manufacturing method of an electronic element module is provided. The method includes: disposing a plurality of first micro-light-emitting diodes on a first temporary substrate; and replacing at least one defective micro-light-emitting diode of the first micro-light-emitting diodes with at least one second micro-light-emitting diode. The first micro-light-emitting diodes and at least one second micro-light-emitting diode are distributed on the first temporary substrate. The first micro-light-emitting diodes and at least one second micro-light-emitting diode have same properties, and at least one of the appearance difference, the height difference and the orientation difference exists between the first micro-light-emitting diodes and at least one second micro-light-emitting diode. A semiconductor structure and a display panel are also provided.Type: ApplicationFiled: December 4, 2023Publication date: March 21, 2024Applicant: PlayNitride Display Co., Ltd.Inventors: Bo-Wei Wu, Yu-Yun Lo, Chien-Chen Kuo, Chang-Feng Tsai, Tzu-Yang Lin
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Publication number: 20240077479Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.Type: ApplicationFiled: August 10, 2023Publication date: March 7, 2024Applicant: DeepBrain Tech. IncInventors: Han-Lin Wang, Chia-Wei Chen, Yao-Wen Liang, Ting-Chun Lin, Yun-Ting Kuo, You-Yin Chen, Yu-Chun Lo, Ssu-Ju Li, Ching-Wen Chang, Yi-Chen Lin
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Patent number: 11922863Abstract: A display panel and a pixel circuit thereof are provided. The pixel circuit includes a driving current generator, a pulse width signal generator, a voltage provider, and a current enabler. The driving current generator provides a driving current. The pulse width signal generator includes an output switch. The output switch is controlled by a control signal, and provides a pulse width signal according to the control signal. The voltage provider adjusts the control signal according to a data write-in signal and a pulse width modulation enable signal. The current enabler provides the driving current to a lighting component according to the pulse width signal and an amplitude modulation enable signal.Type: GrantFiled: December 22, 2022Date of Patent: March 5, 2024Assignee: AUO CorporationInventors: Che-Wei Tung, Mei-Yi Li, Che-Chia Chang, Yu-Chieh Kuo, Yu-Zuo Lin
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Patent number: 11913047Abstract: A method for producing ?-aminobutyric acid includes cultivating, in a culture medium containing glutamic acid or a salt thereof, a probiotic composition including at least one lactic acid bacterial strain selected from the group consisting of Bifidobacterium breve CCFM1025 which is deposited at the Guangdong Microbial Culture Collection Center under an accession number GDMCC 60386, Lactobacillus acidophilus TYCA06, Lactobacillus plantarum LPL28, and Bifidobacterium longum subsp. infantis BLI-02 which are deposited at the China General Microbiological Culture Collection Center respectively under accession numbers CGMCC 15210, CGMCC 17954, and CGMCC 15212, Lactobacillus salivarius subsp. salicinius AP-32 which is deposited at the China Center for Type Culture Collection under an accession number CCTCC M 2011127, and combinations thereof.Type: GrantFiled: January 7, 2022Date of Patent: February 27, 2024Assignee: GLAC BIOTECH CO., LTD.Inventors: Hsieh-Hsun Ho, Ching-Wei Chen, Yu-Fen Huang, Chen-Hung Hsu, Wen-Yang Lin, Yi-Wei Kuo, Shin-Yu Tsai
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Patent number: 11854873Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: GrantFiled: December 6, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Lun Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
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Publication number: 20230377963Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu Lun KE, Yu-Wei KUO, Yi-Wei CHIU, Hung Jui CHANG
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Patent number: 11824288Abstract: A cable connection device is provided. The cable connection device includes a casing, a connection component, a power cable and a circuit board. The casing includes a first accommodation space, a second accommodation space and a channel. The channel is in communication between the first accommodation space and the second accommodation space. The connection component is penetrated through the channel and includes a clamping part disposed in the first accommodation space and a first conductive part disposed in the second accommodation space. Portion of the power cable is disposed in the first accommodation space. The clamping part clamps the power cable and partially pierces the insulating sleeve, so that the clamping part is connected with the wire core. The circuit board is disposed in the second accommodation space and comprises second conductive part. The second conductive part is contacted with the first conductive part.Type: GrantFiled: October 13, 2021Date of Patent: November 21, 2023Assignee: DELTA ELECTRONICS, INC.Inventors: Hung-Sheng Hsieh, Yu-Wei Kuo
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Patent number: 11569125Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: GrantFiled: June 25, 2020Date of Patent: January 31, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
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Patent number: 11557694Abstract: A light emitting device includes: a plurality of light emitting stacked layers, including a first surface and a second surface, wherein the second surface is electrically opposite to the first surface; a mesa structure; a current blocking layer disposed on the first surface, including a sidewall; and a transparent conductive layer disposed on the first surface; and a first pad electrode, disposed on the transparent conductive layer and on the first surface; wherein a retract distance of the transparent conductive layer with respect to an edge of the mesa structure is less than 3 ?m; and wherein a retract distance of the transparent conductive layer with respect to an edge of the sidewall of the current blocking layer is less than 3 ?m.Type: GrantFiled: February 19, 2021Date of Patent: January 17, 2023Assignee: EPISTAR CORPORATIONInventors: Chien Cheng Huang, Kuo-Wei Yen, Yu-Wei Kuo, Yao-Wei Yang, Pei-Hsiang Tseng
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Publication number: 20220416454Abstract: A cable connection device is provided. The cable connection device includes a casing, a connection component, a power cable and a circuit board. The casing includes a first accommodation space, a second accommodation space and a channel. The channel is in communication between the first accommodation space and the second accommodation space. The connection component is penetrated through the channel and includes a clamping part disposed in the first accommodation space and a first conductive part disposed in the second accommodation space. Portion of the power cable is disposed in the first accommodation space. The clamping part clamps the power cable and partially pierces the insulating sleeve, so that the clamping part is connected with the wire core. The circuit board is disposed in the second accommodation space and comprises second conductive part. The second conductive part is contacted with the first conductive part.Type: ApplicationFiled: October 13, 2021Publication date: December 29, 2022Inventors: Hung-Sheng Hsieh, Yu-Wei Kuo
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Publication number: 20220093457Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo
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Patent number: 11195750Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.Type: GrantFiled: November 28, 2018Date of Patent: December 7, 2021Assignee: Tawiwan Semiconductor Manufacturing Co., Ltd.Inventors: Allen Ke, Yi-Wei Chiu, Hung Jui Chang, Yu-Wei Kuo