Abstract: Provided is a content reproduction control system equipped with: a signal characterizing quantity sequence extraction means that, for each content item stored in a content group storage unit that stores at least more than one content item, extracts a signal characterizing quantity sequence which is the sequence of the signal characterizing quantities associated with the content positions on the time axis; a common section group detection means that detects, as a common section group in the signal characterizing quantity sequence for each content item, a common section group for which the signal characterizing quantities for different content items are similar to each other; a content reproduction quality information collection means that, for each common section group, collects content reproduction quality information which indicates the reproduction quality of the content to which each common section of a common section group belongs; and a content reproduction control means that, when the content contained

Abstract: A data receiving device which comprises a decoder which generates a plurality of decoded data based on 1) input data and 2) a plurality of pairs of control data and redundant data, in each the pair, the control data defining a selected encoding process and the redundant data being generated by the selected encoding process based on the control data and the input data, a selection control part which generates an error occurrence information based on information obtained from a medium through which the input data is received, and a selection part which selects output data from the input data and the plurality of decoded data based on the error occurrence information.

Abstract: A method that allows the easy generation of low-density parity-check codes that can realize superior error-correcting characteristics. A processor (50) of a transmission line encoder constructs parity check matrix H from partial matrix H1 of m rows and k columns on the left side and partial matrix H2 of m rows and m columns on the right side. The processor (50) generates partial matrix H2 as a unit matrix. The processor (50) generates partial matrix H1 to satisfy the conditions that, when any two rows contained in partial matrix H1 are selected, the two rows have periods that are relatively prime, or when the periods are identical, the two rows have different phases. The processor (50) then joins partial matrix H1 and partial matrix H2 to generate parity check matrix H.

Abstract: In a content distributing system, a feature amount distributing server 140 includes a processing information generation unit 141 which generates processing information, a feature amount extraction unit 112 which extracts a content feature amount from distributed contents, a processing unit 142 which processes the content feature amount and generates a processed feature amount, a selecting unit 143 which selects an evaluation feature amount from the content feature amount or the processed feature amount, and a distributing unit 144 that distributes the evaluation feature amount to a client 130. A monitoring server 117 has a warning unit which collates the processing information generated by the processing information generation unit 141 of the feature amount distributing server 140 and a quality evaluation value received from the client, and gives a warning when the processing information and the quality evaluation value are mismatched with each other.

Abstract: To provide a dynamic image receiving apparatus which receives dynamic image streams coded with inter-frame prediction such as MPEG from a plurality of channels, and collects the dynamic image streams containing intra-frame coded pictures from each channel in a short time. The dynamic image receiving apparatus includes: a time information accumulative processing device which accumulates code receiving time of the intra-frame coded picture of the dynamic image stream, and periodicity time information containing one of or both of presentation time information and decoding time information contained in the dynamic image stream for each dynamic image stream of the plurality of channels; code receiving time predicting devices which predict the code receiving time of the intra-frame coded pictures based on the periodicity time information; and a channel selection control device which controls channel selection of the dynamic image stream to be received based on the predicted code receiving time information.

Abstract: A method that allows the easy generation of low-density parity-check codes that can realize superior error-correcting characteristics. A processor of a transmission line encoder constructs parity check matrix H from partial matrix H1 of m rows and k columns on the left side and partial matrix H2 of m rows and m columns on the right side. The processor generates partial matrix H2 as a unit matrix. The processor generates partial matrix H1 to satisfy the conditions that, when any two rows contained in partial matrix H1 are selected, the two rows have periods that are relatively prime, or when the periods are identical, the two rows have different phases. The processor then joins partial matrix H1 and partial matrix H2 to generate parity check matrix H.

Abstract: When entropy-encoding a converted quantized amount obtained by converting an image into a frequency region and quantizing it, if the output code bit quantity of the entropy encoding exceeds a predetermined amount, an image obtained by rebuilding the converted quantized value is outputted from an image encoding device. This guarantees an encoding delay caused by re-encoding to be a constant time without increasing the circuit size of the encoding device and provides an image encoding device of a subjectively high quality.

Abstract: A method is disclosed that allows the easy generation of low-density parity-check codes that can realize superior error-correcting characteristics. A processor (50) of a transmission line encoder constructs parity check matrix H from partial matrix H1 of m rows and k columns on the left side and partial matrix H2 of m rows and m columns on the right side. The processor (50) generates partial matrix H2 as a unit matrix. The processor (50) generates partial matrix H1 to satisfy the conditions that, when any two rows contained in partial matrix H1 are selected, the two rows have periods that are relatively prime, or when the periods are identical, the two rows have different phases. The processor (50) then joins partial matrix H1 and partial matrix H2 to generate parity check matrix H.

Abstract: A method is disclosed that allows the easy generation of low-density parity-check codes that can realize superior error-correcting characteristics. A processor (50) of a transmission line encoder constructs parity check matrix H from partial matrix H1 of m rows and k columns on the left side and partial matrix H2 of m rows and m columns on the right side. The processor (50) generates partial matrix H2 as a unit matrix. The processor (50) generates partial matrix H1 to satisfy the conditions that, when any two rows contained in partial matrix H1 are selected, the two rows have periods that are relatively prime, or when the periods are identical, the two rows have different phases. The processor (50) then joins partial matrix H1 and partial matrix H2 to generate parity check matrix H.

Abstract: When audio and video data are transmitted in real-time over a network, a transmission bit rate is controlled depending on the congestion of the network. According to a conventional bit rate control process, the present bit rate is increased or reduced based on the difference between a target value for an amount of data and an observed value of the amount of data. Even if the network is in a steady state, the bit rate is not converged, but is continuously oscillated, tending to deteriorate the quality of transmitted audio and video data. Whereas the bit rate is controlled by only an integral circuit according to the conventional bit rate control process, a bit rate control process according to the present invention is performed using a combination of a proportional circuit and an integral circuit, making it possible to converge the bit rate and hence to prevent the quality of transmitted audio and video data from being lowered due to oscillations of the bit rate.

Abstract: If a reference frame displayed at the reproduction side immediately before a current image frame to be encoded is an inter encoding image frame, a quantization control device (999) appropriately corrects the level (quantization value) of an intra encoding so as to visually reduce I-frame flicker caused by a difference between the inter encoding noise characteristic of the inter encoding image frame and the noise characteristic of the current intra encoding.

Abstract: In the decoder of binary arithmetic code of the present invention, the decoding and reverse binarization of arithmetic code are separated and a large intermediate buffer is interposed. The decoding of arithmetic code is first carried out at the time of input of a stream, whereby the arithmetic code can be decoded at the maximum input bit rate of the decoder. The obtained binary symbol string is first held in the intermediate buffer, following which the reverse binarization from the binary symbol string to multivalued symbols is carried out matched to the processing of the block decoder of the next stage.

Abstract: A data receiving device which comprises a decoder which generates a plurality of decoded data based on 1) input data and 2) a plurality of pairs of control data and redundant data, in each the pair, the control data defining a selected encoding process and the redundant data being generated by the selected encoding process based on the control data and the input data, a selection control part which generates an error occurrence information based on information obtained from a medium through which the input data is received, and a selection part which selects output data from the input data and the plurality of decoded data based on the error occurrence information.

Abstract: A method is disclosed that allows the easy generation of low-density parity-check codes that can realize superior error-correcting characteristics. A processor (50) of a transmission line encoder constructs parity check matrix H from partial matrix H1 of m rows and k columns on the left side and partial matrix H2 of m rows and m columns on the right side. The processor (50) generates partial matrix H2 as a unit matrix. The processor (50) generates partial matrix H1 to satisfy the conditions that, when any two rows contained in partial matrix H1 are selected, the two rows have periods that are relatively prime, or when the periods are identical, the two rows have different phases. The processor (50) then joins partial matrix H1 and partial matrix H2 to generate parity check matrix H.

Abstract: A block dead zone scale generator (202) receives an image signal and a prediction error, analyzes the pattern or prediction performance of a target block, and outputs a dead zone scale suitable for the pattern or prediction performance of the block. A dead zone generator (201) receives a dead zone scale from the block dead zone scale generator (202) and an MB quantization parameter from a quantization control device (103), calculates a dead zone width from the zone scale and the MB quantization parameter, and outputs the dead zone width. A quantization device (102) quantizes an orthogonal transformation coefficient supplied from an orthogonal transformation device (101) by using a dead zone from the dead zone generator (201), and outputs a quantized transformation coefficient.

Abstract: A flow control system include a congestion detecting section and control section. The congestion detecting section detects congestion in a packet switching network. The control section is arranged in a transmitting node. When the congestion detecting section detects congestion, the control section calculates a new transmission packet rate. When the new transmission packet rate is smaller than a current transmission packet rate, the control section changes the current transmission packet rate to the new transmission packet rate after transmission of data to be transmitted to a receiving node. A flow control method is also disclosed.

Abstract: In the decoder of binary arithmetic code of the present invention, the decoding and reverse binarization of arithmetic code are separated and a large intermediate buffer is interposed. The decoding of arithmetic code is first carried out at the time of input of a stream, whereby the arithmetic code can be decoded at the maximum input bit rate of the decoder. The obtained binary symbol string is first held in the intermediate buffer, following which the reverse binarization from the binary symbol string to multivalued symbols is carried out matched to the processing of the block decoder of the next stage.

Abstract: In a data transmission apparatus which performs a bit rate control in accordance with a state of a network, whether a bit rate is changed is determined based on a predetermined probability. By determining a probability value which is used to change a bit rate of each terminal in such a manner that a value obtained by averaging bit rates of all terminals in a communication system becomes a desired bit rate, a control with less fluctuations in bit rate is possible in each terminal, and the quality of real-time communication of, e.g., sounds/image can be improved. Further, the fairness with other control systems such as TCP can be realized.

Abstract: A flow control system include a congestion detecting section and control section. The congestion detecting section detects congestion in a packet switching network. The control section is arranged in a transmitting node. When the congestion detecting section detects congestion, the control section calculates a new transmission packet rate. When the new transmission packet rate is smaller than a current transmission packet rate, the control section changes the current transmission packet rate to the new transmission packet rate after transmission of data to be transmitted to a receiving node. A flow control method is also disclosed.

Abstract: A multiplex data transmission system for transmitting N coded programs having differing bandwidth requirements over M separate channels. The N programs are separately encoded and allocated to the M channels in such a manner that optimum use is made of the available bandwidth in the channels. This is achieved by summing the bandwidth requirements for all the possible distinct combinations of the N programs taken M at a time, and selecting the combination which most closely matches the bandwidth capabilities of the available channels. A multiplexing device generates M separate coded data strings corresponding to the program allocation. At the receiver, a decoder is provided which selectively recovers a user-designated one of the N programs.