Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A cyclical epitaxy process is performed to provide a collector region of a first conductivity type on the collector contact region that is laterally separated from a silicon layer by an air gap. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOI substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOT substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Abstract: A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.

Abstract: A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate.

Abstract: A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate.

Abstract: A layer of a semiconductor material is epitaxially grown on a single-crystal semiconductor structure and on a polycrystalline semiconductor structure. The epitaxial layer is then etched in order to preserve a non-zero thickness of said material on the single-crystal structure and a zero thickness on the polycrystalline structure. The process of growth and etch is repeated, with the same material or with a different material in each repetition, until a stack of epitaxial layers on said single-crystal structure has reached a desired thickness. The single crystal structure is preferably a source/drain region of a transistor, and the polycrystalline structure is preferably a gate of that transistor.

Abstract: A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.

Abstract: A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing by epitaxy a semiconductor layer.

Abstract: A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.

Abstract: The invention relates to a single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.

Abstract: A method for manufacturing an electronic component on a semiconductor substrate, including forming at least one opening in the substrate; forming in the bottom and on the walls of the opening and on the substrate an alternated succession of layers of a first material and of a second material, the second material being selectively etchable with respect to the first material and the substrate; trimming the layer portions of the first material and of the second material which are not located in the opening; selectively etching a portion of the first material to obtain trenches; and filling the trenches with at least one third material.

Abstract: A system and method for producing a single-crystal germanium layer on a dielectric layer by producing a germanium-on-insulator assembly between the surface portions of the third material. The choice of location for these surface portions therefore makes it possible to define the zone on which it is desired to produce the germanium-on-insulator layer. The wafer may be freely chosen between a pure single-crystal silicon wafer and a silicon-on-insulator wafer. A single-crystal germanium first layer is produced on the surface portion of the silicon. The RPCVD produces a partially crystalline germanium first layer. The layer thus comprises various nuclei that have crystallized in possibly different lattices. After carrying out a recrystallization annealing operation, which makes the layer monocrystalline by recrystallizing the various nuclei in one and the same crystal lattice. Thus, the layers are continuous with the single-crystal silicon lattice.

Abstract: The process relates to the production of a layer of a single-crystal first material on a second material. The second material has at least one aperture exposing a surface portion of a single-crystal third material. The process generally includes forming an at least partially crystalline first layer of said first material on said surface portion of the third material. Then, an amorphous or partially crystalline second layer of the first material is formed on the at least partially crystalline first layer of the first material and on one part of the second material that is around said aperture. Finally, the process includes recrystallization annealing of the first material. Thus, it is possible to produce, within one and the same wafer, either transistors on a germanium-on-insulator substrate with transistors on a silicon-on-insulator substrate, or transistors on a germanium-on-insulator substrate with transistors on a silicon substrate.

Abstract: A method for manufacturing an electronic component on a semiconductor substrate, including forming at least one opening in the substrate; forming in the bottom and on the walls of the opening and on the substrate an alternated succession of layers of a first material and of a second material, the second material being selectively etchable with respect to the first material and the substrate; trimming the layer portions of the first material and of the second material which are not located in the opening; selectively etching a portion of the first material to obtain trenches; and filling the trenches with at least one third material.

Abstract: A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing by epitaxy a semiconductor layer.

Abstract: A method for forming, by epitaxy, a heteroatomic single-crystal semiconductor layer on a single-crystal semiconductor wafer, the crystal lattices of the layer and of the wafer being different, including forming, before the epitaxy, in the wafer surface, at least one ring of discontinuities around a useful region.

Abstract: The process relates to the production of a layer of a single-crystal first material on a second material. The second material has at least one aperture exposing a surface portion of a single-crystal third material. The process generally includes forming an at least partially crystalline first layer of said first material on said surface portion of the third material. Then, an amorphous or partially crystalline second layer of the first material is formed on the at least partially crystalline first layer of the first material and on one part of the second material that is around said aperture. Finally, the process includes recrystallization annealing of the first material. Thus, it is possible to produce, within one and the same wafer, either transistors on a germanium-on-insulator substrate with transistors on a silicon-on-insulator substrate, or transistors on a germanium-on-insulator substrate with transistors on a silicon substrate.

Abstract: The invention relates to a single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism

Abstract: A system and method for producing a single-crystal germanium layer on a dielectric layer by producing a germanium-on-insulator assembly between the surface portions of the third material. The choice of location for these surface portions therefore makes it possible to define the zone on which it is desired to produce the germanium-on-insulator layer. The wafer may be freely chosen between a pure single-crystal silicon wafer and a silicon-on-insulator wafer. A single-crystal germanium first layer is produced on the surface portion of the silicon. The RPCVD produces a partially crystalline germanium first layer. The layer thus comprises various nuclei that have crystallized in possibly different lattices. After carrying out a recrystallization annealing operation, which makes the layer monocrystalline by recrystallizing the various nuclei in one and the same crystal lattice. Thus, the layers are continuous with the single-crystal silicon lattice.