Patents by Inventor Yves Campidelli

Yves Campidelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7129563
    Abstract: A process and a device for fabricating a semiconductor device having a gate dielectric made of high-k material, includes a step of depositing, directly on the gate dielectric, a first layer of Si1?xGex, where 0.5<x?1, at a temperature substantially below the temperature at which a poly-Si is deposited by thermal chemical vapor deposition (CVD).
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: October 31, 2006
    Assignee: STMicroelectronics SA
    Inventors: Vincent Cosnier, Yves Morand, Olivier Kermarrec, Daniel Bensahel, Yves Campidelli
  • Publication number: 20040256699
    Abstract: A process and a device for fabricating a semiconductor device having a gate dielectric made of high-k material, includes a step of depositing, directly on the gate dielectric, a first layer of Si1-xGex, where 0.5<x<1, at a temperature substantially below the temperature at which a poly-Si is deposited by thermal chemical vapor deposition (CVD).
    Type: Application
    Filed: April 1, 2004
    Publication date: December 23, 2004
    Applicant: STMICROELECTRONICS SA
    Inventors: Vincent Cosnier, Yves Morand, Olivier Kermarrec, Daniel Bensahel, Yves Campidelli
  • Publication number: 20040250752
    Abstract: A method for forming, by epitaxy, a heteroatomic single-crystal semiconductor layer on a single-crystal semiconductor wafer, the crystal lattices of the layer and of the wafer being different, including forming, before the epitaxy, in the wafer surface, at least one ring of discontinuities around a useful region.
    Type: Application
    Filed: April 1, 2004
    Publication date: December 16, 2004
    Inventors: Daniel Bensahel, Olivier Kermarrec, Yves Morand, Yves Campidelli, Vincent Cosnier
  • Patent number: 6690027
    Abstract: A method for forming on a Ge or Si monocrystalline substrate successive Si/Ge, Si/SiGe, or Si/SiGe/Ge layers for a Ge substrate and inversely for a Si substrate is described. Electrochemical treatment of the stack of layers to make the layers porous and form therein residual crystallites is also described. The invention may be used to provide devices having layers of planes of quantum drops.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: February 10, 2004
    Assignee: France Télécom
    Inventors: Daniel Bensahel, Yves Campidelli, Caroline Hernandez
  • Publication number: 20030221708
    Abstract: Provided is a novel method of cleaning a semiconductor process chamber having deposits on an inner surface thereof. The method involves: (a) introducing a cleaning gas comprising hydrogen chloride into the process chamber, wherein the cleaning gas is effective to react with and remove the deposits from the inner surface of the process chamber; (b) removing gas from the process chamber; and (c) monitoring at least a portion of the removed gas for a species indicative of an endpoint of the chamber cleaning. The invention allows for the cleaning of semiconductor process chambers in an efficient manner so as to reduce process down time and improve process throughput. The method can be applied to in-line analysis.
    Type: Application
    Filed: June 4, 2002
    Publication date: December 4, 2003
    Inventors: Chun-Hao Ly, Yves Campidelli
  • Patent number: 6596555
    Abstract: A method of forming, on a single-crystal semiconductor substrate of a first material, quantum dots of a second material, including growing by vapor phase epitaxy the second material on the first material in optimal conditions adapted to ensuring a growth at a maximum controllable rate. In an initial step, a puff of a gas containing the second material is sent on the substrate, in conditions corresponding to a deposition rate much faster than the maximum controllable rate.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: July 22, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Daniel Bensahel, Olivier Kermarrec, Yves Campidelli
  • Patent number: 6537370
    Abstract: The invention concerns a method which consists in: (a) stabilization of the monocrystalline silicon substrate temperature at a first predetermined temperature T1 of 400 to 500° C.; (b) chemical vapour deposition (CVD) of germanium at said first predetermined temperature T1 until a base germanium layer is formed on the substrate, with a predetermined thickness less than the desired final thickness; (c) increasing the CVD temperature from said first predetermined temperature T1 up to a second predetermined temperature T2 of 750 to 850° C.; and (d) carrying on with CVD of germanium at said second predetermined temperature T2 until the desired final thickness for the monocrystalline germanium final layer is obtained. The invention is useful for making semiconductor devices.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: March 25, 2003
    Assignee: France Télécom
    Inventors: Caroline Hernandez, Yves Campidelli, Daniel Bensahel
  • Patent number: 6429098
    Abstract: The process consists in depositing, by chemical vapour deposition using a mixture of silicon and germanium precursor gases, a single-crystal layer of silicon or germanium on a germanium or silicon substrate by decreasing or increasing the temperature in the range 800-450° C. and at the same time by increasing the Si/Ge or Ge/Si weight ratio from 0 to 100% in the precursor gas mixture, respectively.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: August 6, 2002
    Assignee: France Télécom
    Inventors: Daniel Bensahel, Yves Campidelli, Caroline Hernandez, Maurice Rivoire
  • Patent number: 6399502
    Abstract: The process comprises: etching, in a semiconductor substrate (2), at least one trench (3) with predetermined width and depth; depositing, on the substrate and in the trench, a stack of successive and alternate layers of Si1−xGex (0<x≦1) and Si (5-8), the number and the thickness of which depend on the final use intended for the heterostructure; and chemical-mechanical polishing in order to obtain a final heterostructure having a plane upper main surface, level with which the stack layers deposited in the trench are flush.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: June 4, 2002
    Assignee: France Télécom
    Inventors: Caroline Hernandez, Yves Campidelli, Maurice Rivoire, Daniel Bensahel
  • Patent number: 6372581
    Abstract: A method of nitriding the gate oxide layer of a semiconductor device includes the chemical growth on a silicon substrate of a native silicon oxide layer ≦1 nm thick; treating said substrate coated with the native silicon oxide layer with gas NO at a temperature ≦700° C. and a pressure level ≦104 Pa to obtain a nitrided native silicon oxide layer; and the growth of the gate oxide layer. The method is applicable to PMOS devices. Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the invention. It is to be understood that the forms of the invention shown and described herein are to be taken as the presently preferred embodiments.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: April 16, 2002
    Assignee: France Telecom
    Inventors: Daniel Bensahel, Yves Campidelli, François Martin, Caroline Hernandez
  • Publication number: 20020039833
    Abstract: A method of forming, on a single-crystal semiconductor substrate of a first material, quantum dots of a second material, including growing by vapor phase epitaxy the second material on the first material in optimal conditions adapted to ensuring a growth at a maximum controllable rate. In an initial step, a puff of a gas containing the second material is sent on the substrate, in conditions corresponding to a deposition rate much faster than the maximum controllable rate.
    Type: Application
    Filed: August 3, 2001
    Publication date: April 4, 2002
    Applicant: STMicroelectronics S.A.
    Inventors: Daniel Bensahel, Olivier Kermarrec, Yves Campidelli
  • Patent number: 6255149
    Abstract: A method which includes, prior to depositing the encapsulating silicon layer: A) depositing on the Si1−xGex layer a thin film of amorphous or polycrystalline silicon, then in treating said silicon film with gas nitric oxide at a temperature between 450 to 600° C. and at a pressure level of 104 to 105 Pa to obtain a thin nitrided silicon film; or B) depositing on the Si1−xGex layer a thin film of amorphous or polycrystalline silicon and oxidizing the silicon film to form a surface film of silicon oxide less than 1 nm thick and optionally treating the oxidized amorphous or polycrystalline silicon film with nitric oxide as in A). The invention is applicable to CMOS semiconductors.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: July 3, 2001
    Assignee: France Télécom
    Inventors: Daniel Bensahel, Yves Campidelli, François Martin, Caroline Hernandez
  • Patent number: 6117750
    Abstract: The process consists in depositing, by chemical vapor deposition using a mixture of silicon and germanium precursor gases, a single-crystal layer of silicon or germanium on a germanium or silicon substrate by decreasing or increasing the temperature in the range 800-450.degree. C. and at the same time by increasing the Si/Ge or Ge/Si weight ratio from 0 to 100% in the precursor gas mixture, respectively.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: September 12, 2000
    Assignee: France Telecom
    Inventors: Daniel Bensahel, Yves Campidelli, Caroline Hernandez, Maurice Rivoire
  • Patent number: 4847216
    Abstract: The process consists of depositing at least one layer of a doped material on a heated substrate placed in an enclosure, subjecting the substrate surface to the action of a molecular flux of the material, to the action of a doping particle beam and to the action of an electron beam.
    Type: Grant
    Filed: April 18, 1988
    Date of Patent: July 11, 1989
    Assignee: Centre National d'Etudes des Telecommunications
    Inventors: Francois A. d'Avitaya, Yves Campidelli
  • Patent number: 4643914
    Abstract: Process and apparatus for the growth of films of silicides of refractory metals and films obtained by this process.According to the invention, in order to grow a silicide film of a refractory metal on a silicon substrate, the latter is cleaned, then thermally degassed under an ultra-high vacuum by bringing the substrate to a given temperature between approximately 600.degree. C. and approximately 800.degree. C. A refractory metal is then evaporated on to the substrate at said temperature, after which the temperature is progressively lowered.Application to the production of electronic microcomponents.
    Type: Grant
    Filed: August 6, 1985
    Date of Patent: February 17, 1987
    Inventors: Francois Arnaud D'Avitaya, Yves Campidelli, Roland Pantel