Abstract: The present disclosure relates to integrated circuits, and more particularly, to an anti-tamper x-ray blocking package for secure integrated circuits and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: one or more devices on a front side of a semiconductor material; a plurality of patterned metal layers under the one or more devices, located and structured to protect the one or more devices from an active intrusion; an insulator layer between the plurality of patterned metal layers; and at least one contact providing an electrical connection through the semiconductor material to a front side of the plurality of metals.

Abstract: A structure includes a semiconductor substrate, and a polycrystalline resistor region over the semiconductor substrate. The polycrystalline resistor region includes a semiconductor material in a polycrystalline morphology. A dopant-including polycrystalline region is between the polycrystalline resistor region and the semiconductor substrate.

Abstract: The present disclosure relates to an active x-ray attack prevention structure for secure integrated circuits. In particular, the present disclosure relates to a structure including a functional circuit, and at least one latchup sensitive diode circuit configured to induce a latchup condition in the functional circuit, placed in proximity of the functional circuit.

Abstract: The present disclosure relates to an active x-ray attack prevention structure for secure integrated circuits. In particular, the present disclosure relates to a structure including a functional circuit, and at least one latchup sensitive diode circuit configured to induce a latchup condition in the functional circuit, placed in proximity of the functional circuit.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to optical via connections in chip-to-chip transmission in a 3D chip stack structure using an optical via, and methods of manufacture. The structure has a first wafer, including a first waveguide coupled to an optical resonator in the first wafer, and a second wafer, including a second waveguide, located over the first wafer. The structure also includes an optical via extending between the optical resonator of the first wafer and the second waveguide of the second wafer to optically couple the first and second waveguides.

Abstract: Integrated optical structures include a first wafer layer, a first insulator layer directly connected to the top of the first wafer layer, a second wafer layer directly connected to the top of the first insulator layer, a second insulator layer directly connected to the top of the second wafer layer, and a third wafer layer directly connected to the top of the second insulator layer. Such structures include: a first optical waveguide positioned within the second wafer layer; an optical coupler positioned within the second wafer layer, the second insulator layer, and the third wafer layer; and a second optical waveguide positioned within the third wafer layer. The optical coupler transmits an optical beam from the first optical waveguide to the second optical waveguide through the second insulator layer.

Abstract: Various particular embodiments include a primary waveguide including an end section; cantilevered waveguides, each cantilevered waveguide including an end section disposed adjacent the end section of the primary waveguide; and control pins for applying an electrical bias to the cantilevered waveguides to selectively displace the end sections of the cantilevered waveguides away from the end section of the primary waveguide.

Abstract: Integrated optical structures include a first wafer layer, a first insulator layer directly connected to the top of the first wafer layer, a second wafer layer directly connected to the top of the first insulator layer, a second insulator layer directly connected to the top of the second wafer layer, and a third wafer layer directly connected to the top of the second insulator layer. Such structures include: a first optical waveguide positioned within the second wafer layer; an optical coupler positioned within the second wafer layer, the second insulator layer, and the third wafer layer; and a second optical waveguide positioned within the third wafer layer. The optical coupler transmits an optical beam from the first optical waveguide to the second optical waveguide through the second insulator layer.

Abstract: Various particular embodiments include a primary waveguide including an end section; cantilevered waveguides, each cantilevered waveguide including an end section disposed adjacent the end section of the primary waveguide; and control pins for applying an electrical bias to the cantilevered waveguides to selectively displace the end sections of the cantilevered waveguides away from the end section of the primary waveguide.

Abstract: In an approach to fabricating a silicon on insulator wafer, one or more semiconductor device elements are implanted and one or more shallow trench isolations are formed on a top surface of a first semiconductor wafer. A first dielectric material layer is deposited over the top surface of the first semiconductor wafer, filling the shallow trench isolations. A dielectric material layer on a bottom surface of a second semiconductor wafer is bonded to a dielectric material layer on the top of the first semiconductor wafer and one or more semiconductor devices are formed on a top surface of the second semiconductor wafer. Then, one or more through silicon vias are created connecting the one or more semiconductor devices on the top surface of the second semiconductor wafer and the one or more semiconductor device elements on the top surface of the first semiconductor wafer.

Abstract: Various embodiments include an integrated circuit having: at least one waveguide disposed in a low refractive index layer; a splitter connected to the at least one waveguide, the splitter consisting of at least two signal paths; an optical signal detector connected to an end of each of the at least two signal paths; and an electrical disconnect member connected to each optical signal detector.

Abstract: In an approach to fabricating a silicon on insulator wafer, one or more semiconductor device elements are implanted and one or more shallow trench isolations are formed on a top surface of a first semiconductor wafer. A first dielectric material layer is deposited over the top surface of the first semiconductor wafer, filling the shallow trench isolations. A dielectric material layer on a bottom surface of a second semiconductor wafer is bonded to a dielectric material layer on the top of the first semiconductor wafer and one or more semiconductor devices are formed on a top surface of the second semiconductor wafer. Then, one or more through silicon vias are created connecting the one or more semiconductor devices on the top surface of the second semiconductor wafer and the one or more semiconductor device elements on the top surface of the first semiconductor wafer.

Abstract: Disclosed are an interdigitated capacitor and an interdigitated vertical native capacitor, each having a relatively low (e.g., zero) net coefficient of capacitance with respect to a specific parameter. For example, the capacitors can have a zero net linear temperature coefficient of capacitance (Tcc) to limit capacitance variation as a function of temperature or a zero net quadratic voltage coefficient of capacitance (Vcc2) to limit capacitance variation as a function of voltage. In any case, each capacitor can incorporate at least two different plate dielectrics having opposite polarity coefficients of capacitance with respect to the specific parameter due to the types of dielectric materials used and their respective thicknesses. As a result, the different dielectric plates will have opposite effects on the capacitance of the capacitor that cancel each other out such that the capacitor has a zero net coefficient of capacitance with respect to specific parameter.

Abstract: Disclosed are an interdigitated capacitor and an interdigitated vertical native capacitor, each having a relatively low (e.g., zero) net coefficient of capacitance with respect to a specific parameter. For example, the capacitors can have a zero net linear temperature coefficient of capacitance (Tcc) to limit capacitance variation as a function of temperature or a zero net quadratic voltage coefficient of capacitance (Vcc2) to limit capacitance variation as a function of voltage. In any case, each capacitor can incorporate at least two different plate dielectrics having opposite polarity coefficients of capacitance with respect to the specific parameter due to the types of dielectric materials used and their respective thicknesses. As a result, the different dielectric plates will have opposite effects on the capacitance of the capacitor that cancel each other out such that the capacitor has a zero net coefficient of capacitance with respect to specific parameter.