ACTIVE ATTACK PREVENTION FOR SECURE INTEGRATED CIRCUITS USING LATCHUP SENSITIVE DIODE CIRCUIT
The present disclosure relates to an active x-ray attack prevention structure for secure integrated circuits. In particular, the present disclosure relates to a structure including a functional circuit, and at least one latchup sensitive diode circuit configured to induce a latchup condition in the functional circuit, placed in proximity of the functional circuit.
The present disclosure relates to integrated circuits, and more particularly, to an active x-ray attack prevention device for securing integrated circuits and methods of operation.
BACKGROUNDWhen using active x-ray spectrum analysis, a party can observe an integrated circuit under power and a voltage contrast and determine a functional state of the design. Further, it is possible to unlock a private key of devices once the decrypting step has been passed and the register is first used. A known technique to prevent such unlocking can encompass package shielding, but this is still prone to tampering. Accordingly, known techniques have not been able to prevent uncovering of key technology and intellectual property in an integrated circuit.
SUMMARYIn an aspect of the disclosure, a structure includes a functional circuit, and at least one latchup sensitive diode circuit configured to induce a latchup condition in the functional circuit, placed in proximity of the functional circuit.
In another aspect of the disclosure, a structure includes a plurality of functional circuits cascaded across a chip, and a plurality of latchup sensitive diode circuits which comprise a P-N diode circuit to induce a cascading latchup condition and is cascaded in a predetermined proximity of the functional circuits across the chip.
In another aspect of the disclosure, a method includes inducing a latchup condition which turns off a power supply to a functional circuit in response to a current in the functional circuit being above a predetermined threshold.
The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
The present disclosure relates to integrated circuits, and more particularly, to an active x-ray attack prevention device for securing integrated circuits and methods of operation. More specifically, the present disclosure provides an in-built laser interrogation protection circuit component which includes circuits susceptible to a latchup placed in close proximity to functional circuits. By implementing the devices disclosed herein, circuits can latchup when induced by an x-ray illumination from a scanning electron microscope (SEM) or a backside attack. Accordingly and advantageously, by implementing the devices disclosed herein, the devices can prevent an active x-ray attack from determining a functional state of a circuit design and prevent the theft of key technology and intellectual property.
In known circuits, an attack and/or analysis can occur on a circuit from scanning a backside of a chip across a die. The attack and/or analysis can capture the function of the device which can then be re-constructed. For example, the analysis can be done through active and passive optical probing using photo emission (PE), electro-optical frequency modulation, or laser voltage techniques. To avoid the attack and/or analysis on a circuit, a charge trap logic structure can be used. However, in this type of circuit, the attack and/or analysis can occur after the charge trap device has been bypassed. Further, package shielding can prevent the attack and/or analysis on a circuit; however, the package shielding is susceptible to tampering. In contrast, the present disclosure provides an in-built laser interrogation protection circuit which can latchup from illumination from the SEM or backside attack.
In particular, complementary metal-oxide-semiconductor (CMOS) circuits are prone to latchup. In known CMOS circuits, special layouts and ground rules are used to avoid a latchup condition. In the present disclosure, though, a latchup condition is deliberately designed into the chip which is initiated by generating a large number of carriers in close proximity to a circuit. For example, the latchup condition can occur by creating lots of charges due to light irradiation from a backside attack using a scanning electron microscope (SEM). Therefore, structures sensitive to the latchup condition can be placed in close proximity or connected to the functional circuits to prevent an attack.
In other circuits, photodiodes are used across a chip to detect a backside attack. In particular, a voltage sensing circuit is used to detect a change in resistance when a photodiode is “ON” to generate a tamper signal. Multiple other known circuits utilize photodiodes, which directly generate a tamper signal under illumination. In contrast, in the present disclosure, photodiodes are used across a chip to prevent the backside attack (instead of simply detecting the backside attack) by placing the photodiodes in close proximity to the functional chips. In particular, in the present disclosure, under illumination, the photodiodes will result in a latchup condition of all of the functional chips.
In
In embodiments, an N+ region 130 and a P+ region 140 are formed within the N-well 120. Further, a power supply 160 (e.g., the power supply 160 being at a VDD level) is connected to the N+ region 130 and a ground 150 is connected to the P+ region 140. Further, the N-well 120, the N+ region 130, and the P+ region 140 can be represented by a diode 170 (i.e., P-N diode 170, as shown in
The N-well 120, the N+ region 130, and the P+ region 140 can be formed by conventional ion implantation processes known to those of skill in the art. For example, the N-well 120 may be formed by introducing a dopant by, for example, ion implantation that includes a concentration of a dopant in the substrate 110. The different regions 130, 140 may be formed by introducing a concentration of a different dopant or opposite conductivity type in the substrate 110. In embodiments, respective patterned implantation masks may be used to define selected areas exposed for the implantations. The implantation mask used to select the exposed area for forming the well is stripped after implantation, and before the implantation mask used to form the well. Similarly, the implantation mask used to select the exposed area for forming the well is stripped after the implantation is performed. The implantation masks may include a layer of a light-sensitive material, such as an organic photoresist, applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. Each of the implantation masks has a thickness and stopping power sufficient to block mask areas against receiving a dose of the implanted ions. The N-well 120 is doped with n-type dopants, e.g., Arsenic (As), Phosphorus (P), and Sb, among other suitable examples. The N+ region 130 is doped with a higher concentration of n-type dopants than the N-well 120. The P+ region is doped with p-type dopants, e.g., Boron (B).
In
The device 500 of
Still referring to
The functional circuit 310 (e.g., CMOS inverter) comprises the resistors 440, 450 and the bipolar junction transistors 460, 470. The functional circuit 310 is connected to the circuit 300 through a connection 490 (also shown in
The device 700 of
In
The circuit and the method of operation for an active x-ray attack preventing for secure integrated circuits of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the circuit and the method for an active x-ray attack preventing for secure integrated circuits of the present disclosure has been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the circuit and the method for an active x-ray attack preventing for secure integrated circuits uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
The active x-ray attack device can be utilized in system on chip (SoC) technology. It should be understood by those of skill in the art that SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as Smartphones) and edge computing markets. SoC is also commonly used in embedded systems and the Internet of Things.
The structures and methods as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims
1. A structure, comprising:
- a functional circuit; and
- at least one latchup sensitive diode circuit configured to induce a latchup condition in the functional circuit, placed in proximity of the functional circuit,
- wherein the at least one latchup sensitive diode circuit comprises a P-N diode circuit, and
- the P-N diode circuit comprises an N-well which includes an N+ region and a P+ region.
2. The structure of claim 1, wherein the functional circuit comprises a CMOS inverter.
3.-4. (canceled)
5. A structure, comprising:
- a functional circuit; and
- at least one latchup sensitive diode circuit configured to induce a latchup condition in the functional circuit, placed in proximity of the functional circuit,
- wherein the at least one latchup sensitive diode circuit comprises a P-N diode circuit, and
- the P-N diode circuit comprises at least two N-wells with a first N-well including a N+ region and a P+ region and a second N-well including two N+ regions.
6. The structure of claim 5, wherein the N+ region of the first N-well is electrically connected to the N+ region of the second N-well.
7. The structure of claim 5, further comprising an e-fuse which turns off a power supply to the functional circuit in response to the latchup condition.
8. The structure of claim 1, wherein the P-N diode circuit induces the latchup condition in the functional circuit in response to an illumination of the P-N diode circuit from a backside of the structure.
9. The structure of claim 8, further comprising an e-fuse which turns off a power supply to the functional circuit in response to the latchup condition.
10. The structure of claim 1, wherein the P-N diode circuit is connected to a plurality of inverters.
11. The structure of claim 1, wherein the at least one latchup sensitive diode circuit is connected to a parasitic bipolar PNP transistor.
12. The structure of claim 1, wherein the at least one latchup sensitive diode circuit induces the latchup condition in the functional circuit in response to an illumination of the at least one sensitive diode circuit from a backside of the structure.
13. A structure, comprising:
- a plurality of functional circuits cascaded across a chip; and
- a plurality of latchup sensitive diode circuits which each comprise a P-N diode circuit to induce a cascading latchup condition and is cascaded in a predetermined proximity of the functional circuits across the chip,
- wherein the P-N diode circuit comprises an N-well which includes an N+ region and a P+ region.
14. The structure of claim 13, wherein each of the plurality of latchup sensitive diode circuits is connected to a plurality of inverters.
15. The structure of claim 14, wherein the plurality of latchup sensitive diode circuits induce the cascading latchup condition across the chip in response to an illumination of the plurality of latchup sensitive diode circuits from a backside of the structure.
16. The structure of claim 15, further comprising an e-fuse which turns off a power supply to the functional circuit in response to the latchup condition.
17. The structure of claim 13, wherein each of the plurality of latchup sensitive diode circuits is connected to a parasitic bipolar PNP transistor.
18. The structure of claim 17, wherein the plurality of latchup sensitive diode circuits induce the cascading latchup condition across the chip in response to an illumination of the plurality of latchup sensitive diode circuits from a backside of the structure.
19. The structure of claim 17, further comprising an e-fuse which turns off a power supply in response to the latchup condition.
20. (canceled)
Type: Application
Filed: Apr 22, 2020
Publication Date: Oct 28, 2021
Inventors: Vibhor JAIN (Williston, VT), Ajay RAMAN (Essex Junction, VT), Sebastian T. VENTRONE (South Burlington, VT), John J. ELLIS-MONAGHAN (Grand Isle, VT), Siva P. ADUSUMILLI (Burlington, VT), Yves T. NGU (Williston, VT)
Application Number: 16/855,185