Abstract: In a method of data transmission according to one embodiment of the invention, signals on adjacent conductive paths pass through different sequences of inversions and regenerations. In an apparatus according to one embodiment of the invention, two sets of parallel transmission lines include series of inverting and non-inverting buffers having different sequences.

Abstract: A reticle and method simultaneously generate small- and large-scale circuit structures of a parallel processing system. The reticle includes at least two circuit traces having respective contact pads within an overlap zone of the reticle. Connectivity between a circuit trace of one reticle image with a circuit trace of an adjacent reticle image is controlled by varying the degree of overlap between the two images.

Abstract: A communications bus enables communication of data signals in a parallel processing system having a plurality of substantially identical cells, each cell having an access point for transmitting data signals into the communications bus. The communications bus includes a plurality of parallel channels, and at least one channel crossover point associated with each cell. Each crossover point implements a regular change in a channel order of the communications bus, such that each access point is coupled to a channel of the communications bus. Propagation delays are reduced by inserting buffers at regular intervals along the length of each channel. An output buffer at a downstream boundary of each power domain of the system prevents undesired currents due to voltage mismatch. The propagation direction of data signals away from the access point, and propagation of data to an adjacent downstream cell can be controlled to reduce bus traffic and power consumption.

Abstract: In a method of data transmission according to one embodiment of the invention, signals on adjacent conductive paths pass through different sequences of inversions and regenerations. In an apparatus according to one embodiment of the invention, two sets of parallel transmission lines include series of inverting and non-inverting buffers having different sequences.

Abstract: In a method of data transmission according to one embodiment of the invention, data transitions on adjacent conductors are separated in time. In one such method, a plurality of sets of input signals is received, and a plurality of sets of corresponding output signals is transmitted. One set of the output signals is delayed with respect to another set by a delay period T_DLY. In another such method, the output signals are transmitted and received on the same semiconductor substrate.

Abstract: In a method of data transmission according to one embodiment of the invention, data transitions having the same clock dependence are separated in space. In one such method, signals of one set are transmitted on corresponding conductive paths in one direction, signals of another set are transmitted on corresponding conductive paths in the other direction, and adjacent conductive paths that each carry a signal of one set are separated by at least one conductive path that carries a signal of another set. In an apparatus according to one embodiment of the invention, the conductive paths are fabricated on a semiconductor substrate.

Abstract: A highly robust fault tolerant scan chain is designed for scanning (and/or controlling a configuration of) a parallel processing system. The scan chain implements parallel redundant scan chains that follow physically diverse paths through the parallel processing system. For each IC under test, a set of redundant TAPs perform a boundary scan, and the test results are combined by voting. The TAPs of each set are physically diverse, in that they are physically located in separate power domains of the parallel processing system. As a result, the scan chain is robust to faults affecting power and/or control signal supply to any one power domain. Respective input and output dummy cells at opposite extreme ends of the scan chain provide a graceful separation and recombination of the redundant parallel scan chains, and so renders the architecture of the scan chain transparent to external boundary scan circuit elements.

Abstract: In a method of data transmission according to one embodiment of the invention, data transitions on adjacent conductors are separated in time. In a method of data transmission according to another embodiment of the invention, signals on adjacent conductive paths pass through different alternating sequences of inversions and regenerations. In a method of data transmission according to a further embodiment of the invention, data transitions having the same clock dependence are separated in space.

Abstract: The invention relates to a method of iteratively, selectively tuning the impedance of integrated semiconductor devices, by modifying the dopant profile of a region of low dopant concentration by controlled diffusion of dopants from one or more adjacent regions of higher dopant concentration through the melting action of a focussed heating source, for example a laser. In particular the method is directed to increasing the dopant concentration of the region of lower dopant concentration, but may also be adapted to decrease the dopant concentration of the region.

Abstract: It is common that the presence of a defect causes abnormal gate output voltage excursions in data buffers, AND gates, OR gates and multiplexers in current-mode logic circuits. A voltage excursion is detected by a voltage excursion detection apparatus which includes a built-in detector. The detector, which is little overhead, is used to monitor output swings of all gates (differential circuits) and flags all abnormal voltage excursions. These detection results cover classes of faults that cannot be tested by stuck-at testing methods only. The voltage detection apparatus works well below "at-speed" frequencies.

Abstract: A multicomputer chip has a common bus and up to ten microcomputers connected in parallel to the common bus via routers contained in the microcomputers. The common bus can be connected to an external bus by means of a router mounted on or off the chip. Any defective computer found during testing can be rendered inactive by assigning it an unused address and, in this way, the remaining computers are unaffected. Instead of providing each multicomputer on a separate chip, a complete wafer may be manufactured so that it contains many of the multicomputers. A hierarchical bus system interconnects the multicomputers so as to permit efficient routing of data between the various computers.