Patents by Inventor Zailong Bian
Zailong Bian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11626481Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.Type: GrantFiled: October 11, 2021Date of Patent: April 11, 2023Assignee: Micron Technology, Inc.Inventors: Zailong Bian, Janos Fucsko
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Publication number: 20220028865Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.Type: ApplicationFiled: October 11, 2021Publication date: January 27, 2022Applicant: Micron Technology, Inc.Inventors: Zailong Bian, Janos Fucsko
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Patent number: 11171205Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.Type: GrantFiled: March 9, 2020Date of Patent: November 9, 2021Assignee: Micron Technology, Inc.Inventors: Zailong Bian, Janos Fucsko
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Publication number: 20200212175Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.Type: ApplicationFiled: March 9, 2020Publication date: July 2, 2020Applicant: Micron Technology, Inc.Inventors: Zailong Bian, Janos Fucsko
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Patent number: 10622442Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.Type: GrantFiled: November 26, 2018Date of Patent: April 14, 2020Assignee: Micron Technology, Inc.Inventors: Zailong Bian, Janos Fucsko
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Patent number: 10319678Abstract: A three dimensional or stacked circuit device includes a conductive channel cap on a conductor channel. The channel cap can be created via selective deposition or other process to prevent polishing down the conductive material to isolate the contacts. The conductor channel extends through a deck of multiple tiers of circuit elements that are activated via a gate. The gate is activated by electrical potential in the conductor channel. The conductive cap on the conductor channel can electrically connect the conductor channel to a bitline or other signal line, and/or to another deck of multiple circuit elements.Type: GrantFiled: December 22, 2015Date of Patent: June 11, 2019Assignee: Intel CorporationInventors: Hongqi Li, Gowrisankar Damarla, Roger Lindsay, Zailong Bian, Jin Lu, Shyam Ramalingam, Prasanna Srinivasan
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Publication number: 20190096994Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.Type: ApplicationFiled: November 26, 2018Publication date: March 28, 2019Inventors: Zailong Bian, Janos Fucsko
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Patent number: 10170545Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.Type: GrantFiled: February 13, 2018Date of Patent: January 1, 2019Assignee: Micron Technology, Inc.Inventors: Zailong Bian, Janos Fucsko
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Patent number: 10147727Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.Type: GrantFiled: February 13, 2018Date of Patent: December 4, 2018Assignee: Micron Technology, Inc.Inventors: Jaydeb Goswami, Zailong Bian, Yushi Hu, Eric R. Blomiley, Jaydip Guha, Thomas Gehrke
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Publication number: 20180175039Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.Type: ApplicationFiled: February 13, 2018Publication date: June 21, 2018Applicant: Micron Technology, Inc.Inventors: Jaydeb Goswami, Zailong Bian, Yushi Hu, Eric R. Blomiley, Jaydip Guha, Thomas Gehrke
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Publication number: 20180175145Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.Type: ApplicationFiled: February 13, 2018Publication date: June 21, 2018Inventors: Zailong Bian, Janos Fucsko
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Publication number: 20180138182Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.Type: ApplicationFiled: November 11, 2016Publication date: May 17, 2018Inventors: Jaydeb Goswami, Zailong Bian, Yushi Hu, Eric R. Blomiley, Jaydip Guha, Thomas Gehrke
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Patent number: 9972628Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.Type: GrantFiled: November 11, 2016Date of Patent: May 15, 2018Assignee: Micron Technology, Inc.Inventors: Jaydeb Goswami, Zailong Bian, Yushi Hu, Eric R. Blomiley, Jaydip Guha, Thomas Gehrke
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Patent number: 9929233Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.Type: GrantFiled: December 20, 2016Date of Patent: March 27, 2018Assignee: Micron Technology, Inc.Inventors: Zailong Bian, Janos Fucsko
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Patent number: 9754879Abstract: A method of fabricating integrated circuitry includes forming a first conductive line. First elemental tungsten is deposited directly against an elevationally outer surface of the first conductive line selectively relative to any exposed non-conductive material. Dielectric material is formed elevationally over the first conductive line and a via is formed there-through to conductive material of the first conductive line at a location where the first tungsten was deposited. Second elemental tungsten is non-selectively deposited to within the via and electrically couples to the first conductive line. A second conductive line is formed elevationally outward of and electrically coupled to the second tungsten that is within the via.Type: GrantFiled: January 11, 2016Date of Patent: September 5, 2017Assignee: Micron Technology, Inc.Inventor: Zailong Bian
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Publication number: 20170133585Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments.Type: ApplicationFiled: January 19, 2017Publication date: May 11, 2017Inventors: Muralikrishnan Balakrishnan, Zailong Bian, Gowrisankar Damarla, Hongqi Li, Jin Lu, Shyam Ramalingam, Xiaoyun Zhu
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Publication number: 20170104059Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.Type: ApplicationFiled: December 20, 2016Publication date: April 13, 2017Inventors: Zailong Bian, Janos Fucsko
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Patent number: 9577192Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments.Type: GrantFiled: May 21, 2014Date of Patent: February 21, 2017Assignee: Sony Semiconductor Solutions CorporationInventors: Muralikrishnan Balakrishnan, Zailong Bian, Gowrisankar Damarla, Hongqi Li, Jin Lu, Shyam Ramalingam, Xiaoyun Zhu
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Patent number: 9559163Abstract: The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.Type: GrantFiled: September 8, 2014Date of Patent: January 31, 2017Assignee: Micron Technology, Inc.Inventors: Zailong Bian, Janos Fucsko
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Publication number: 20160247756Abstract: A three dimensional or stacked circuit device includes a conductive channel cap on a conductor channel. The channel cap can be created via selective deposition or other process to prevent polishing down the conductive material to isolate the contacts. The conductor channel extends through a deck of multiple tiers of circuit elements that are activated via a gate. The gate is activated by electrical potential in the conductor channel. The conductive cap on the conductor channel can electrically connect the conductor channel to a bitline or other signal line, and/or to another deck of multiple circuit elements.Type: ApplicationFiled: December 22, 2015Publication date: August 25, 2016Inventors: Hongqi Li, Gowrisankar Damarla, Roger Lindsay, Zailong Bian, Jin Lu, Shyam Ramalingam, Prasanna Srinivasan