Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to determine a scheduling policy of one or more blocks of one or more threads.

Abstract: Apparatuses, systems, and techniques including application programming interfaces (APIs), compilers, and instructions to allocate a number of registers per thread, to deallocate a number of allocated registers for a thread, and to allocate a number of registers per function. For example, a processor performs an API to indicate a number of registers to allocate to a thread when performing matrix multiplication operations on a graphics processing unit (GPU). As another example, a processor performs an API to indicate a number of registers to allocate to a function.

Abstract: Apparatuses, systems, and techniques to execute programs in a single hardware context on a graphics processing unit (GPU). In at least one embodiment, resource management patches expressed in library or executable code are applied to one or more kernels to ensure execution in a shared context on a GPU.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate one or more attributes of one or more groups of blocks of one or more threads.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to cause memory to be shared between two or more groups of blocks of threads.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to determine which of two or more blocks of threads are to be scheduled in parallel.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate two or more blocks of threads to be scheduled in parallel.

Abstract: Apparatuses, systems, and techniques to perform third party management of operational thread memory requests within one or more processors by use of a server to manage said memory and memory requests to perform dynamic memory allocation during runtime without overwrite risk, according to at least one embodiment. In at least one embodiment, processor scomprising one or more circuits to cause one or more threads to use one or more virtual storage location addresses to access one or more physical storage locations based, at least in part, on information indicating whether the one or more physical storage locations are allocated to the one or more threads.

Abstract: Apparatuses, systems, and techniques to execute software programs. In at least one embodiment, an application programming interface (API) is performed to cause one or more kernel attributes to be indicated to one or more users based, at least in part, on one or more user-provided identifiers of the one or more kernel attributes.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate one or more attributes of one or more groups of blocks of one or more threads.

Abstract: Apparatuses, systems, and techniques to execute programs in a single hardware context on a graphics processing unit (GPU). In at least one embodiment, resource management patches expressed in library or executable code are applied to one or more kernels to ensure execution in a shared context on a GPU.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to cause memory to be shared between two or more groups of blocks of threads.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to determine which of two or more blocks of threads are to be scheduled in parallel.

Abstract: Apparatuses, systems, and techniques to enable a program to access data regardless of where said data is stored. In at least one embodiment, a system enables a program to access data regardless of where said data is stored, based on, for example, one or more locations encoding one or more addresses of said data.

Abstract: Apparatuses, systems, and techniques to cause one or more software kernels to be performed based, at least in part, on a data structure to indicate one or more attributes of the one or more software kernels. In at least one embodiment, one or more software kernels are caused to be performed based, at least in part, on a data structure to indicate one or more attributes of the one or more software kernels based on, for example, CUDA or other parallel computing platform code.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate two or more blocks of threads to be scheduled in parallel.

Abstract: Apparatuses, systems, and techniques to execute software programs. In at least one embodiment, an application programming interface (API) is performed to cause one or more kernel attributes to be indicated to one or more users based, at least in part, on one or more user-provided identifiers of the one or more kernel attributes.