Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to cause performance of one or more threads within a group of blocks of threads to stop at least until all threads within the group of blocks have performed a barrier instruction.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate a scheduling policy of one or more blocks of one or more threads.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate a maximum number of blocks of threads capable of being scheduled in parallel.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to determine which of two or more blocks of threads are to be scheduled in parallel.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate whether one or more threads within a group of blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to determine a scheduling policy of one or more blocks of one or more threads.

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate one or more limitations of one or more attributes of one or more groups of blocks of one or more threads.

Abstract: A new level(s) of hierarchy—Cooperate Group Arrays (CGAs)—and an associated new hardware-based work distribution/execution model is described. A CGA is a grid of thread blocks (also referred to as cooperative thread arrays (CTAs)). CGAs provide co-scheduling, e.g., control over where CTAs are placed/executed in a processor (such as a GPU), relative to the memory required by an application and relative to each other. Hardware support for such CGAs guarantees concurrency and enables applications to see more data locality, reduced latency, and better synchronization between all the threads in tightly cooperating collections of CTAs programmably distributed across different (e.g., hierarchical) hardware domains or partitions.

Abstract: A processor supports new thread group hierarchies by centralizing work distribution to provide hardware-guaranteed concurrent execution of thread groups in a thread group array through speculative launch and load balancing across processing cores. Efficiencies are realized by distributing grid rasterization among the processing cores.

Abstract: Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache.

Abstract: In various embodiments, scheduling dependencies associated with tasks executed on a processor are decoupled from data dependencies associated with the tasks. Before the completion of a first task that is executing in the processor, a scheduling dependency specifying that a second task is dependent on the first task is resolved based on a pre-exit trigger. In response to the resolution of the scheduling dependency, the second task is launched on the processor.

Abstract: Apparatuses, systems, and techniques to enable a program to access data regardless of where said data is stored. In at least one embodiment, a system enables a program to access data regardless of where said data is stored, based on, for example, one or more locations encoding one or more addresses of said data.

Abstract: Various embodiments include a parallel processing computer system that provides multiple memory synchronization domains in a single parallel processor to reduce unneeded synchronization operations. During execution, one execution kernel may synchronize with one or more other execution kernels by processing outstanding memory references. The parallel processor tracks memory references for each domain to each portion of local and remote memory. During synchronization, the processor synchronizes the memory references for a specific domain while refraining from synchronizing memory references for other domains. As a result, synchronization operations between kernels complete in a reduced amount of time relative to prior approaches.

Abstract: Apparatuses, systems, and techniques to control operation of a memory cache. In at least one embodiment, cache guidance is specified within application source code by associating guidance with declaration of a memory block, and then applying specified guidance to source code statements that access said memory block.

Abstract: Apparatuses, systems, and techniques to execute programs in a single hardware context on a graphics processing unit (GPU). In at least one embodiment, resource management patches expressed in library or executable code are applied to one or more kernels to ensure execution in a shared context on a GPU.

Abstract: The present invention relates to methods for the conversion of the substrate specificity of desaturases. Specifically, the present invention pertains to a method for the conversion of the substrate specificity of a ?5 and/or ?6 desaturase to the substrate specificity of a ?4 desaturase, the method comprising: identifying regions and/or amino acid residues which control the substrate specificity of (i) the ?5 and/or ?6 desaturase and (ii) the ?4 desaturase; and replacing in the amino acid sequence of the mentioned ?5 and/or ?6 desaturase, the regions and/or amino acid residues which control the substrate specificity of the ?5 and/or ?6 desaturase, by the corresponding regions and/or amino acid residues which control the substrate specificity of the ?4 desaturase, thereby converting the substrate specificity of the ?5 and/or ?6 desaturase to the substrate specificity of the ?4 desaturase.

Abstract: The present invention relates to methods for the conversion of the substrate specificity of desaturases. Specifically, the present invention pertains to a method for the conversion of the substrate specificity of a ?5 and/or ?6 desaturase to the substrate specificity of a ?4 desaturase, the method comprising: identifying regions and/or amino acid residues which control the substrate specificity of (i) the ?5 and/or ?6 desaturase and (ii) the ?4 desaturase; and replacing in the amino acid sequence of the mentioned ?5 and/or ?6 desaturase, the regions and/or amino acid residues which control the substrate specificity of the ?5 and/or ?6 desaturase, by the corresponding regions and/or amino acid residues which control the substrate specificity of the ?4 desaturase, thereby converting the substrate specificity of the ?5 and/or ?6 desaturase to the substrate specificity of the ?4 desaturase.

Abstract: The present invention relates to methods for the conversion of the substrate specificity of desaturases. Specifically, the present invention pertains to a method for the conversion of the substrate specificity of a ?5 and/or ?6 desaturase to the substrate specificity of a ?4 desaturase, the method comprising: identifying regions and/or amino acid residues which control the substrate specificity of (i) the ?5 and/or ?6 desaturase and (ii) the ?4 desaturase; and replacing in the amino acid sequence of the mentioned ?5 and/or ?6 desaturase, the regions and/or amino acid residues which control the substrate specificity of the ?5 and/or ?6 desaturase, by the corresponding regions and/or amino acid residues which control the substrate specificity of the ?4 desaturase, thereby converting the substrate specificity of the ?5 and/or ?6 desaturase to the substrate specificity of the ?4 desaturase.

Abstract: One embodiment relates to a method of treating cancer by administering a compound of Formula I to a patient.

Abstract: A method of setting hot key includes: triggering an RBSU setting procedure in a system code interface of a BIOS of the computing apparatus, executing the RBSU setting procedure to enter an RBSU setting interface, registering a captured hot key in the RBSU setting interface and establishing a screen image procedure code with respect to the captured hot key. A method of capturing a screen image for applying the foregoing method in a RBSU executing interface includes: triggering an RBSU executing procedure under the system code interface, executing the RBSU executing procedure to enter the RBSU executing interface, determining if the captured hot key is triggered in the RBSU executing interface, executing the screen image procedure code to capture a screen image of the RBSU executing interface if positive, and storing the screen image into a storage apparatus electrically coupled with the computing apparatus.