Abstract: The present disclosure relates to an imaging device, a pixel and a method thereof The imaging device comprises: a pixel array, which comprises multiple pixels arranged in rows and columns, wherein at least one pixel comprises multiple subpixels, and the multiple subpixels share one floating diffusion region; and a control circuit, which controls the pixel array; wherein the control circuit reads the multiple subpixels one by one under the rolling shutter state, and reads the multiple subpixels simultaneously under the global shutter state.

Abstract: Disclosed are a pixel unit, and an imaging method and apparatus thereof. The pixel has a first and a second pixel sub-portion each comprising one or more photodiodes; one or more transfer transistors each coupled to a floating diffusion, for transferring the charges generated by the one or more photodiodes in response to incident light during an exposure period and accumulated in the photodiode during said exposure period respectively to the floating diffusion; a reset transistor; and a source follower transistor coupled to the floating diffusion for amplifying and outputting the pixel signal of the floating diffusion. In some embodiments, the pixel further includes a capacitor and a gain control transistor.

Abstract: Disclosed are a pixel unit, and an imaging method and apparatus thereof. The pixel comprises a first and a second pixel sub-portion each comprising one or more photodiodes; one or more transfer transistors each coupled to a floating diffusion, for transferring the charges generated by the one or more photodiodes in response to incident light during an exposure period and accumulated in the photodiode during said exposure period respectively to the floating diffusion; a reset transistor; and a source follower transistor coupled to the floating diffusion for amplifying and outputting the pixel signal of the floating diffusion. In some embodiments, the pixel further includes a capacitor and a gain control transistor.

Abstract: Disclosed are a pixel unit, and an imaging method and apparatus thereof. The pixel has a first and a second pixel sub-portion each comprising one or more photodiodes; one or more transfer transistors each coupled to a floating diffusion, for transferring the charges generated by the one or more photodiodes in response to incident light during an exposure period and accumulated in the photodiode during said exposure period respectively to the floating diffusion; a reset transistor; and a source follower transistor coupled to the floating diffusion for amplifying and outputting the pixel signal of the floating diffusion. In some embodiments, the pixel further includes a capacitor and a gain control transistor.

Abstract: A pixel cell and row select and row driver circuits include two column bias circuits and row driver circuits, one placed at the right and one placed at the left side of the array of pixel cells. The digital control signals for the two sets of bias and row driver circuits enter at the center top or bottom of the array of pixel cells and drive the circuits symmetrically. The combination of two-sided row driver and column bias helps eliminate any signal delay and bias difference between the left and right side of the pixel cell array. More significantly this circuit construction can minimize horizontal shading in the resulting image.

Abstract: An image sensor array of shared pixel units fabricated by a CMOS technology, wherein each pixel unit includes a plurality of photodiodes and respective transfer transistors and floating drains whose layout constitutes mirror images. The plurality of photodiodes each share a single reset transistor and source follower amplifier transistor wherein the shared floating diode is spaced at the minimum distance from a gate electrode of the source follower transistor as is allowed by the CMOS fabrication technology chosen to manufacture the image sensor array.

Abstract: An image sensor array of shared pixel units fabricated by a CMOS technology, wherein each pixel unit includes a plurality of photodiodes and respective transfer transistors and floating drains whose layout constitutes mirror images. The plurality of photodiodes each share a single reset transistor and source follower amplifier transistor wherein the shared floating diode is spaced at the minimum distance from a gate electrode of the source follower transistor as is allowed by the CMOS fabrication technology chosen to manufacture the image sensor array.

Abstract: An image sensor array of shared pixel units fabricated by a CMOS technology, wherein each pixel unit includes a plurality of photodiodes and respective transfer transistors and floating drains whose layout constitutes mirror images. The plurality of photodiodes each share a single reset transistor and source follower amplifier transistor wherein the shared floating diode is spaced at the minimum distance from a gate electrode of the source follower transistor as is allowed by the CMOS fabrication technology chosen to manufacture the image sensor array.

Abstract: An image sensor array of shared pixel units fabricated by a CMOS technology, wherein each pixel unit includes a plurality of photodiodes and respective transfer transistors and floating drains whose layout constitutes mirror images. The plurality of photodiodes each share a single reset transistor and source follower amplifier transistor wherein the shared floating diode is spaced at the minimum distance, from a gate electrode of the source follower transistor as is allowed by the CMOS fabrication technology chosen to manufacture the image sensor array.

Abstract: A rectangular image sensor array of shared pixel units fabricated by a CMOS technology, wherein each pixel unit has a photodiode, a transfer transistor, a floating drain, a source follower transistor, a reset transistor and an in-pixel ground contact. The floating diode is spaced at the minimum distance from a gate electrode of the source follower transistor as is allowed by the CMOS fabrication technology chosen to manufacture the image sensor array.

Abstract: An improved DNA sequencing system comprising a DNA sample holder residing on a stacked BSI global shutter image sensor illuminated by a pulsed laser for fluorescent illumination detection. The pulsed laser has on and off periods wherein during the laser on period a Fluorophore tag attached to a DNA sample is excited to produce fluorescence emission while the imaging system captures no illumination and during the off period the global shutter imaging system captures persistent fluorescent emission from the DNA sample and reads out an imaging signal.

Abstract: A pixel cell and row select and row driver circuits include two column bias circuits and row driver circuits, one placed at the right and one placed at the left side of the array of pixel cells. The digital control signals for the two sets of bias and row driver circuits enter at the center top or bottom of the array of pixel cells and drive the circuits symmetrically. The combination of two-sided row driver and column bias helps eliminate any signal delay and bias difference between the left and right side of the pixel cell array. More significantly this circuit construction can minimize horizontal shading in the resulting image.

Abstract: A pixel cell and readout circuit includes an anti-eclipse voltage clamp circuit at both the top and bottom of each column line of an array of the pixel cells. The anti-eclipse voltage clamp circuits form a row with each column in the array coupled to an anti-eclipse voltage clamp circuit. The combination of two rows of anti-eclipse voltage clamp circuits helps settle the clamp voltage more rapidly and to compensate for the increased length of the anti-eclipse voltage circuit row as well as the column line resistance due to narrow metal lines and increased numbers of pixels as well as the requirement to operate a sensor at a higher frame rate. More significantly this circuit construction can minimize vertical shading in the resulting image.

Abstract: An improved DNA sequencing system comprising a DNA sample holder residing on a stacked BSI global shutter image sensor illuminated by a pulsed laser for fluorescent illumination detection. The pulsed laser has on and off periods wherein during the laser on period a Fluorophore tag attached to a DNA sample is excited to produce fluorescence emission while the imaging system captures no illumination and during the off period the global shutter imaging system captures persistent fluorescent emission from the DNA sample and reads out an imaging signal.

Abstract: A pixel cell has a large and small photodiode, transfer transistors, a reset transistor, a dynamic range enhancement capacitor, a capacitor control transistor, a storage capacitor, a storage capacitor control transistor, an amplifier transistor in a source follower configuration and a rolling shutter row select transistor and a readout circuit block. The small and large photodiodes are exposed simultaneously, the large photodiode having a constant exposure while the small photodiode has a chopped exposure and charge transfer to a storage capacitor.

Abstract: A pixel cell has a large and small photodiode, transfer transistors, a reset transistor, a dynamic range enhancement capacitor, a capacitor control transistor, a storage capacitor, a storage capacitor control transistor, an amplifier transistor in a source follower configuration and a rolling shutter row select transistor and a readout circuit block. The small and large photodiodes are exposed simultaneously, the large photodiode having a constant exposure while the small photodiode has a chopped exposure and charge transfer to a storage capacitor.

Abstract: An image sensor has a pixel cell array comprising clusters of pixel cell blocks each block having four pixel cells under the same microlens and filter wherein during readout electrical signals from two pixels positioned along a first diagonal are binned followed by binning the signals from two pixels positioned along the remaining second reverse diagonal in order to reduce spatial color artifacts associated with orthogonal binning schemes and minimize gaps or irregular spacing between optical centers within an image read out from the array of pixel cells.

Abstract: Disclosed are a pixel unit, an apparatus thereof, and a method thereof. The pixel unit comprises a first and a second transfer transistors with different photosensitive areas coupled to a floating diffusion and transfer the charges generated by a first and a second photodiodes in response to incident light during an exposure period and accumulated in the photodiode during said exposure period thereto; a capacitor with a first end coupled to a specified voltage; a gain control transistor coupled between the second end of the capacitor and the floating diffusion for imposing an isolation control therebetween; a reset transistor coupled to the second end of the capacitor and the gain control transistor for resetting the level of the coupling point therebetween via a reset control signal; and a source follower transistor coupled to the floating diffusion for amplifying and outputting the pixel signals.

Abstract: Disclosed are a pixel unit, and an imaging method and apparatus thereof. The pixel comprises a first and a second pixel sub-portion each comprising one or more photodiodes; one or more transfer transistors each coupled to a floating diffusion, for transferring the charges generated by the one or more photodiodes in response to incident light during an exposure period and accumulated in the photodiode during said exposure period respectively to the floating diffusion; a reset transistor; and a source follower transistor coupled to the floating diffusion for amplifying and outputting the pixel signal of the floating diffusion. In some embodiments, the pixel further includes a capacitor and a gain control transistor.

Abstract: The present invention relates to an imaging apparatus, which comprises: a pixel array, comprising a plurality of pixels arranged in rows and columns, wherein at least one of the pixels comprises: a first capacitor configured to store a reset signal, and a second capacitor configured to store a pixel signal; a plurality of column circuits, wherein at least one of the column circuits reads the reset signal from the first capacitor, reads the pixel signal from the second capacitor, and generates difference between the reset signal and the pixel signal, wherein the pixel is configured to store the pixel signal to the second capacitor after the reset signal is stored to the first capacitor.