Abstract: An image sensor has global shutter imaging pixel cells, each including an anti-blooming transistor gate for modifying electric charge within a photodiode and for setting the photodiode to a selected potential. The sensor also has a row decoder circuit providing readout signals to each row of the imaging cells during both a readout interval and during a calibration interval for each row and providing to the anti-blooming transistor drain a selectable potential supply voltage. A mode select switch within the row decoder circuit applies either a standard drain supply voltage or an adjustable low voltage to the anti-blooming transistor drain. A programmable function logic circuit determines the timing of operation of the mode select switch to provide knee-point calibration to minimize photo conversion variations that lead to fixed pattern noise.

Abstract: An image sensor has a stacked pixel arrangement including both rolling and global shutter readout circuits wherein each pixel includes an adjustable transfer transistor gate voltage level for modifying electric charge within a photodiode during exposure depending on incident light intensity. The sensor also has a row decoder circuit providing readout signals to each row of the imaging cells during both a readout interval and during a calibration interval for each row. The row decoder may employ one of several of its features to provide a self-knee point calibration following an image signal readout in order to minimize photo conversion variations that lead to fixed pattern noise and to enhance dynamic range.

Abstract: The present disclosure relates to an imaging device, a pixel and a method thereof. The imaging device comprises: a pixel array, which comprises multiple pixels arranged in rows and columns, wherein at least one pixel comprises multiple subpixels, and the multiple subpixels share one floating diffusion region; and a control circuit, which controls the pixel array; wherein the control circuit reads the multiple subpixels one by one under the rolling shutter state, and reads the multiple subpixels simultaneously under the global shutter state.

Abstract: A pixel cell has four maskless phase detection photodiodes sharing the same readout amplifier, microlens and filter color. The four photodiodes are configured to operate in two adjacent pairs wherein the two adjacent pairs of photodiodes are separated by a light guide and are positioned under the single microlens such that light incident in a first direction is collected in a first pair of photodiodes of the two adjacent pairs of photodiodes and light incident in a second direction is collected in a second pair of photodiodes of the two adjacent pairs of photodiodes. The microlens has a plano-convex shape which causes light to be incident in two directions on photodiodes positioned under each of two sides of the microlens.

Abstract: A pixel cell has four maskless phase detection photodiodes sharing the same readout amplifier, microlens and filter color. The four photodiodes are configured to operate in two adjacent pairs wherein the two adjacent pairs of photodiodes are separated by a light guide and are positioned under the single microlens such that light incident in a first direction is collected in a first pair of photodiodes of the two adjacent pairs of photodiodes and light incident in a second direction is collected in a second pair of photodiodes of the two adjacent pairs of photodiodes. The microlens has a plano-convex shape which causes light to be incident in two directions on photodiodes positioned under each of two sides of the microlens.

Abstract: The present invention relates to an imaging apparatus, including a pixel array comprising a plurality of pixels arranged in rows and columns, wherein at least one of the pixels comprises: a first capacitor configured to store a reset signal, and a second capacitor configured to store a pixel signal; a plurality of column circuits, wherein at least one of the column circuits reads the reset signal from the first capacitor, reads the pixel signal from the second capacitor, and generates difference between the reset signal and the pixel signal, wherein the pixel is configured to store the pixel signal to the second capacitor after the reset signal is stored to the first capacitor.

Abstract: A pixel cell has a photodiode, a transfer transistor, a reset transistor, an amplifier transistor and a readout circuit block. The photodiode, transfer transistor, reset transistor and amplifier transistor are disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode and converting the image charge to an image signal. The readout circuit block is disposed within a second substrate of a second semiconductor chip and the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings. The global shutter readout mode provides in-pixel correlated double sampling.

Abstract: A pixel cell has a photodiode, a transfer transistor, a reset transistor, a dynamic range enhancement capacitor, a capacitor control transistor, an amplifier transistor in a source follower configuration and a rolling shutter row select transistor and a readout circuit block. The photodiode, a transfer transistor, a reset transistor, dynamic range enhancement capacitor, capacitor control transistor, amplifier transistor and rolling shutter row select transistor are disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit block may be partially disposed within a second substrate of a second semiconductor chip and partially disposed within the first substrate wherein the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings.

Abstract: A pixel cell has a photodiode, a readout circuit, a vertical transfer transistor and a reflective structure. The photodiode is disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit is disposed within a second substrate of a second semiconductor chip. The vertical transfer transistor is coupled between the photodiode and the readout circuitry to transfer the image charge from the photodiode to the readout circuitry. The reflective structure is positioned between the readout circuit and the photodiode to reflect incident light, that passes through the photodiode without being absorbed, back towards the photodiode for a second chance at being absorbed.

Abstract: The present invention relates to an imaging apparatus, including a pixel array comprising a plurality of pixels arranged in rows and columns, wherein at least one of the pixels comprises a capacitor configured to store a reset signal and a pixel signal; and a plurality of column circuits, wherein at least one of the column circuits reads the reset signal and the pixel signal from the capacitor respectively, and generates the difference between the reset signal and the pixel signal, the generation of the pixel signal being later than that of the reset signal.

Abstract: A pixel cell has a photodiode, a readout circuit, a vertical transfer transistor and a reflective structure. The photodiode is disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit is disposed within a second substrate of a second semiconductor chip. The vertical transfer transistor is coupled between the photodiode and the readout circuitry to transfer the image charge from the photodiode to the readout circuitry. The reflective structure is positioned between the readout circuit and the photodiode to reflect incident light, that passes through the photodiode without being absorbed, back towards the photodiode for a second chance at being absorbed.

Abstract: A pixel cell has a photodiode, a transfer transistor, a reset transistor, an amplifier transistor and a readout circuit block. The photodiode, transfer transistor, reset transistor and amplifier transistor are disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode and converting the image charge to an image signal. The readout circuit block is disposed within a second substrate of a second semiconductor chip and the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings. The global shutter readout mode provides in-pixel correlated double sampling.

Abstract: A pixel cell has a photodiode, a transfer transistor, and a readout circuit block. The photodiode, transfer transistor, and reset transistor are disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit block is disposed within a second substrate of a second semiconductor chip and the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings. The global shutter readout mode provides in-pixel correlated double sampling.

Abstract: A pixel cell has a photodiode, a transfer transistor, a reset transistor, a dynamic range enhancement capacitor, a capacitor control transistor, an amplifier transistor in a source follower configuration and a rolling shutter row select transistor and a readout circuit block. The photodiode, a transfer transistor, a reset transistor, dynamic range enhancement capacitor, capacitor control transistor, amplifier transistor and rolling shutter row select transistor are disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit block may be partially disposed within a second substrate of a second semiconductor chip and partially disposed within the first substrate wherein the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings.

Abstract: A pixel cell has a photodiode, a transfer transistor, a reset transistor, an amplifier transistor in a source follower configuration, and a readout circuit block. The photodiode, transfer transistor, reset transistor and source follower amplifier are disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit block may be partially disposed within a second substrate of a second semiconductor chip and partially disposed within the first substrate wherein the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings. The global shutter readout mode provides in-pixel correlated double sampling.

Abstract: An imaging system with a pixel cell has a photodiode, a transfer transistor, a reset transistor, an amplifier transistor in a source follower configuration, and a readout circuit block. The photodiode, transfer transistor, reset transistor and source follower amplifier are part of an array disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit block may be partially disposed within a second substrate of a second semiconductor chip and partially disposed within the first substrate wherein the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings. The global shutter readout mode provides in-pixel correlated double sampling.

Abstract: A pixel cell has a photodiode, a readout circuit, and a vertical transfer transistor. The photodiode is disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit is disposed within a second substrate of a second semiconductor chip. The vertical transfer transistor is coupled between the photodiode and the readout circuitry to transfer the image charge from the photodiode to the readout circuitry.

Abstract: A pixel cell has a photodiode, a transfer transistor, a reset transistor, an amplifier transistor in a common source configuration and a readout circuit block. The photodiode, transfer transistor, reset transistor and common source amplifier are disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit block may be partially disposed within a second substrate of a second semiconductor chip and partially disposed within the first substrate wherein the readout circuit block comprises optionally selectable rolling shutter and global shutter readout modes through the use of computer programmable digital register settings. The global shutter readout mode provides in-pixel correlated double sampling.

Abstract: The present invention relates to an imaging apparatus, including a pixel array comprising a plurality of pixels arranged in rows and columns, wherein at least one of the pixels comprises: a first capacitor configured to store a reset signal, and a second capacitor configured to store a pixel signal; a plurality of column circuits, wherein at least one of the column circuits reads the reset signal from the first capacitor, reads the pixel signal from the second capacitor, and generates difference between the reset signal and the pixel signal, wherein the pixel is configured to store the pixel signal to the second capacitor after the reset signal is stored to the first capacitor.

Abstract: The present invention relates to an imaging apparatus, including a pixel array comprising a plurality of pixels arranged in rows and columns, wherein at least one of the pixels comprises a capacitor configured to store a reset signal and a pixel signal; and a plurality of column circuits, wherein at least one of the column circuits reads the reset signal and the pixel signal from the capacitor respectively, and generates the difference between the reset signal and the pixel signal, the generation of the pixel signal being later than that of the reset signal.