Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable description' s of the circuit.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: Image sensor with a successive approximation A/D converter that automatically compensates for black level and provides a signal indicative of the difference between the reset level and the signal level. Black level for each of a plurality of color pixels may be obtained. This may be obtained from, for example, an image sensor with intentionally darkened pixels. Levels from these pixels are sampled, and an average of these pixels is used to form a black level for similarly-colored pixels. That black level is stored, and used to drive a D/A converter. Another D/A converter forms the actual conversion, and is compared to a reference. The reference is selected such that the output signal is automatically compensated for black level, and also corresponds to the difference between signal and reset.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: An electronic device is provided such as a programmable rise/fall time control circuit, for example, that delivers a continuous and near linear rising/falling slope of a control signal, with programmability that can be implemented in future CMOS image sensor devices. This device includes a programmability block for reset or transfer gate signals. The programmability block includes two inputs: an input bias current and a signal from the control bits. The programmability block further includes two similar internal circuit blocks, one for generating a fall time control signal, and one for generating a rise time control signal. Additionally the programmability block includes two outputs; a fall time control signal, and a rise time control signal. The device further includes a reset or transfer gate buffer configured as an inverter. The reset or transfer gate buffer includes three input signals: The fall time control signal and rise time control signal from the programmability block, and an INT Reset signal.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: In a digital memory system, systems and methods that control a logical value and an integrity of data represented by charge are provided. In one embodiment, a bit line is coupled to the cell. A voltage generator is arranged to generate a plurality of cell operating voltages varying in response to a voltage control signal. A controller generates a control signal, stores a predetermined one of logical values in a cell by generating a series of operating voltages, transmits the series of operating voltages, and determines whether the predetermined one of the logical values has been stored in the cell in response to a voltage on the bit line. The controller includes a charge integrity estimating module and determines whether the predetermined one of the logical values has been stored in the cell by initiating the operation of the charge integrity estimating module.

Abstract: A digital memory system (30) includes a memory cell (10), a bit line (12), a voltage generator (320) and a controller (90). The controller is arranged to store a predetermined logical value in the cell by generating a series of the operating voltages beginning with the first voltage and continuing with successively larger operating voltages greater the first voltage. The voltages are transmitted to the cell from the voltage generator. After each transmittal of one of the series of operating voltages, the controller causes at least a portion of the charge stored in the cell to flow in the bit line. The controller determines whether the predetermined one of the logical values has been stored in the cell in response to the flow of charge. The controller terminates transmittal of the series of operating voltages to the cell in the event that the predetermined one of the logical states has been stored or in the event that one of the series of successively larger operating voltages equals the second voltage.

Abstract: A digital memory system (30) includes a memory cell (10), a bit line (12), a voltage generator (320) a controller (90) and a charge integrity estimating module (135). A series of successively larger operating voltages are transmitted to the cell from the voltage generator. The controller determines whether a predetermined value has been stored in the cell. The charge integrity estimating module detects the quantity of charge in the memory cell, for example, by using a sense amplifier (170).

Abstract: A digital memory system (30) includes a memory cell (10), a bit line (12), a voltage generator (320) and a controller (90). The controller is arranged to store a predetermined logical value in the cell by generating a series of the operating voltages beginning with the first voltage and continuing with successively larger operating voltages greater the first voltage. The voltages are transmitted to the cell from the voltage generator. After each transmittal of one of the series of operating voltages, the controller causes at least a portion of the charge stored in the cell to flow in the bit line. The controller determines whether the predetermined one of the logical values has been stored in the cell in response to the flow of charge. The controller terminates transmittal of the series of operating voltages to the cell in the event that the predetermined one of the logical states has been stored or in the event that one of the series of successively larger operating voltages equals the second voltage.