Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.

Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.

Abstract: A storage system with temperature control. The system includes a plurality of storage devices such as solid state drives, a system controller such as a baseboard management controller, and one or more cooling fans. Each storage devices includes a controller configured to estimate the heat load in the storage device and/or an effective temperature, resulting from operations performed in the storage device. The system controller employs active disturbance rejection control to adjust the fan speed based on the estimated heat loads, the estimated temperatures, and/or the sensed internal temperatures, of the storage devices.

Abstract: A system and method for active disturbance rejection based thermal control is configured to receive, at a first active disturbance rejection thermal control (ADRC) controller, a first temperature measurement from a first thermal zone. The ADRC controller generates a first output control signal for controlling a first cooling element, wherein the first output control signal is generated according a first estimated temperature and a first estimated disturbance calculated by a first extended state observer (ESO) of the first ADRC controller.

Abstract: A memory module includes a module error interface, a module data interface, and a plurality of memory device. The module error interface communicates error information a system control path. The module data interface communicates data to and from a main memory path that is separate from the system control path. Each memory device includes a device controller, a device error interface and a device data interface in which the error data interface is separate from the device data interface. Each device controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the corresponding memory device to generate corrected data, generate error information, communicate the error information through the device error interface to the module error interface, and communicate the corrected data through the device data interface to the module data interface. The ECC controller records the error information.

Abstract: An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface.

Abstract: Exemplary embodiments include a socket interposer having a plurality of connectors configured to attach to a server board, the server board including: a first processor socket having a processor form factor, and a first memory associated with the first processor socket, a processor inserted into the at least first processor socket, the processor having access to the first memory, and a second processor socket having the processor form factor, and a second memory associated with the second processor socket, wherein the plurality of connectors are configured to fit the processor form factor; and a multi-modal I/O interface having a first mode and a second mode, wherein in the first mode provides processor-to-processor communication, and the second mode provides the first processor with accessibility to the second memory associated with the second processor socket.

Abstract: A computing system providing high-availability access to computing resources includes: a plurality of interfaces; a plurality of sets of computing resources, each of the sets of computing resources including a plurality of computing resources; and at least three switches, each of the switches being connected to a corresponding one of the interfaces via a host link and being connected to a corresponding one of the sets of computing resources via a plurality of resource connections, each of the switches being configured such that data traffic is distributed to remaining ones of the switches through a plurality of cross-connections between the switches if one of the switches fails.

Abstract: Embodiments of the inventive concept include a non-volatile memory module array system. The system can include non-volatile memory modules each including a first port, a second port, solid state drives, a switch, and a port configuration logic section. The system can include a bus connected to the first or second ports. The system can include a host to communicate with the non-volatile memory modules via the bus. The port configuration logic section can toggle between a first port configuration associated with the second port and a second port configuration associated with the second port. The port configuration logic section can include a first non-volatile configuration section to store the first and second port configurations associated with the second port. The first port configuration can cause the second port to operate as a downstream port. The second port configuration can cause the second port to operate as an upstream port.

Abstract: Embodiments of the inventive concept include a plurality of memory ranks, a buffer chip including a rank remap control section configured to remap a rank from among the plurality of memory ranks of the volatile memory module responsive to a failure of the rank, and a dynamic serial presence detect section configured to dynamically update a stated total capacity of the volatile memory module based at least on the remapped rank. In some embodiments, a memory module includes a plurality of memory ranks, an extra rank in addition to the plurality of memory ranks, the extra rank being a spare rank configured to store a new page corresponding to a failed page from among the plurality of ranks, and a buffer chip including a page remap control section configured to remap the failed page from among the plurality of ranks to the new page in the extra rank.

Abstract: An electronic system includes: a storage device configured to receive a host command including: a system interface unit, a device controller, coupled to the system interface unit, configured to analyze the host command, a near-field wireless transceiver, coupled to the device controller, configured to communicate through a wireless link, and a non-volatile storage array, coupled to the device controller, configured to store user data for transfer through the system interface unit or the near-field wireless transceiver; wherein: the device controller can configure the near-field wireless transceiver for identifying a multi-hop map; and the near-field wireless transceiver is configured to hand-off the host command through the wireless link.

Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.

Abstract: Embodiments of the inventive concept include a non-volatile memory module array system. The system can include non-volatile memory modules each including a first port, a second port, solid state drives, a switch, and a port configuration logic section. The system can include a bus connected to the first or second ports. The system can include a host to communicate with the non-volatile memory modules via the bus. The port configuration logic section can toggle between a first port configuration associated with the second port and a second port configuration associated with the second port. The port configuration logic section can include a first non-volatile configuration section to store the first and second port configurations associated with the second port. The first port configuration can cause the second port to operate as a downstream port. The second port configuration can cause the second port to operate as an upstream port.

Abstract: Embodiments of the inventive concept include solid state drive (SSD) multi-card adapters that can include multiple solid state drive cards, which can be incorporated into existing enterprise servers without major architectural changes, thereby enabling the server industry ecosystem to easily integrate evolving solid state drive technologies into servers. The SSD multi-card adapters can include an interface section between various solid state drive cards and drive connector types. The interface section can perform protocol translation, packet switching and routing, data encryption, data compression, management information aggregation, virtualization, and other functions.

Abstract: Embodiments of the inventive concept include 2.5 inch hard disk drive form factor solid state drive multi-card adapters that can include multiple M.2 solid state drive cards, which can be incorporated into existing enterprise servers without major architectural changes, thereby enabling the server industry ecosystem to easily integrate M.2 solid state drive technology into servers. Multiple M.2 solid state drive cards and a peripheral component interconnect express (PCIe) switch can be included within a 2.5 inch hard disk drive form factor solid state drive multi-card adapter. The solid state drive multi-card adapters can be attached to or seated within drive bays of a computer server that supports non-volatile memory express (NVMe) 2.5 inch drives without any changes to the server architecture, thereby providing a straight-forward upgrade path.

Abstract: Embodiments of the inventive concept include Open Cloud Server (OCS)-compliant and other enterprise servers having high-density modular non-volatile flash memory blades and associated multi-card modules. A modular non-volatile flash memory blade can be seated within a 1U tray. The flash memory blade can include a server motherboard and multiple non-volatile flash memory blade multi-card modules. Each of the multi-card modules can include a printed circuit board, a switch coupled to the printed circuit board, a module power port, an input/output port, and riser card slots to receive solid state drive riser cards. The solid state drive riser cards can be seated within a corresponding riser card slot of the multi-card modules, and can each include multiple solid state drive chips. The server motherboard can communicate with the solid state drive chips via the cable connector riser cards and associated cables.

Abstract: Embodiments of the inventive concept include a plurality of memory ranks, a buffer chip including a rank remap control section configured to remap a rank from among the plurality of memory ranks of the volatile memory module responsive to a failure of the rank, and a dynamic serial presence detect section configured to dynamically update a stated total capacity of the volatile memory module based at least on the remapped rank. In some embodiments, a memory module includes a plurality of memory ranks, an extra rank in addition to the plurality of memory ranks, the extra rank being a spare rank configured to store a new page corresponding to a failed page from among the plurality of ranks, and a buffer chip including a page remap control section configured to remap the failed page from among the plurality of ranks to the new page in the extra rank.

Abstract: Embodiments of the present inventive concept relate to systems and methods for dynamically allocating and/or redistributing thermal budget to each memory group in a memory array from a total memory thermal budget based on the workload of each memory group. In this manner, the memory groups having a higher workload can receive a higher thermal budget. The allocation can be dynamically adjusted over time. Thus, the individual and overall memory group performance increases while efficiently allocating the total thermal budget. By dynamically sharing the total thermal budget of the system, the performance of the system as a whole is increased, thereby lowering, for example, the total cost of ownership (TCO) of datacenters.

Abstract: Embodiments of the present inventive concept relate to systems and methods for dynamically allocating and/or redistributing thermal budget to each processor from a total processor thermal budget based on the workload of each processor. In this manner, the processor(s) having a higher workload can receive a higher thermal budget. The allocation can be dynamically adjusted over time. The individual and overall processor performance increases while efficiently allocating the total thermal budget. By dynamically sharing the total thermal budget of the system, the performance of the system as a whole is increased, thereby lowering, for example, the total cost of ownership (TCO) of datacenters.

Abstract: An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface.