Patents by Inventor Zhanping Chen
Zhanping Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11476190Abstract: Embodiments herein describe techniques for fuse lines and plugs formation. A semiconductor device may include a fuse line having a nominal fuse segment abutted to a necked fuse segment. The nominal fuse segment may be wider than the necked fuse segment. A first spacer may be along a first side of the fuse line and a second spacer along a second side opposite to the first side of the fuse line. The first spacer may include a part having a width at least twice a width of a part of the second spacer. A plug within a vicinity of the necked fuse segment may have a plug width that may be at least twice a plug with of a plug of an interconnect line outside the vicinity. Other embodiments may also be described and claimed.Type: GrantFiled: December 30, 2016Date of Patent: October 18, 2022Assignee: Intel CorporationInventors: Balijeet S. Bains, Charles H. Wallace, Zhanping Chen
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Patent number: 11239149Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate and coupled to a first contact and a second contact. The first contact and the second contact may be above the metal interconnect and in contact with the metal interconnect. A first resistance may exist between the first contact and the second contact through the metal interconnect. After a programming voltage is applied to the second contact while the first contact is coupled to a ground terminal to generate a current between the first contact and the second contact, a non-conducting barrier may be formed as an interface between the second contact and the metal interconnect. A second resistance may exist between the first contact, the metal interconnect, the second contact, and the non-conducting barrier. Other embodiments may be described and/or claimed.Type: GrantFiled: April 2, 2018Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Vincent Dorgan, Jeffrey Hicks, Uddalak Bhattacharya, Zhanping Chen, Walid Hafez
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Publication number: 20210104459Abstract: Embodiments herein describe techniques for fuse lines and plugs formation. A semiconductor device may include a fuse line having a nominal fuse segment abutted to a necked fuse segment. The nominal fuse segment may be wider than the necked fuse segment. A first spacer may be along a first side of the fuse line and a second spacer along a second side opposite to the first side of the fuse line. The first spacer may include a part having a width at least twice a width of a part of the second spacer. A plug within a vicinity of the necked fuse segment may have a plug width that may be at least twice a plug with of a plug of an interconnect line outside the vicinity. Other embodiments may also be described and claimed.Type: ApplicationFiled: December 30, 2016Publication date: April 8, 2021Inventors: BALIJEET S. BAINS, CHARLES H. WALLACE, ZHANPING CHEN
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Publication number: 20190304893Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate and coupled to a first contact and a second contact. The first contact and the second contact may be above the metal interconnect and in contact with the metal interconnect. A first resistance may exist between the first contact and the second contact through the metal interconnect. After a programming voltage is applied to the second contact while the first contact is coupled to a ground terminal to generate a current between the first contact and the second contact, a non-conducting barrier may be formed as an interface between the second contact and the metal interconnect. A second resistance may exist between the first contact, the metal interconnect, the second contact, and the non-conducting barrier. Other embodiments may be described and/or claimed.Type: ApplicationFiled: April 2, 2018Publication date: October 3, 2019Inventors: Vincent DORGAN, Jeffrey HICKS, Uddalak BHATTACHARYA, Zhanping CHEN, Walid M. HAFEZ
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Publication number: 20180145083Abstract: The controlled modification of an antifuse programming voltage is described. In one example, an antifuse circuit is formed on a substrate, including a gate area of the antifuse circuit. A molecule is implanted into the gate area to damage the structure of the gate area. Electrodes are formed over the gate areas to connect the antifuse circuit to other components.Type: ApplicationFiled: June 25, 2015Publication date: May 24, 2018Inventors: Xiaoghong TONG, Walid M. HAFEZ, Zhiyong MA, Peng BAI, Chia-Hong JAN, Zhanping CHEN
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Patent number: 9679845Abstract: Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied fuse programming voltage may open necked fuse segments to affect operation of an IC. In embodiments, the fuse structure includes a pair of neighboring interconnect lines equidistant from a center interconnect line. In further embodiments, the center interconnect line, and at least one of the neighboring interconnect lines, include line segments of lateral widths that differ by a same, and complementary amount. In further embodiments, the center interconnect line is interconnected at opposite ends of a necked line segment. In further embodiments, the necked line segment is fabricated with pitch-reducing spacer-based patterning process.Type: GrantFiled: May 8, 2014Date of Patent: June 13, 2017Assignee: Intel CorporationInventors: Zhanping Chen, Andrew W. Yeoh, Seongtae Jeong, Uddalak Bhattacharya, Charles H. Wallace
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Publication number: 20170018499Abstract: Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied fuse programming voltage may open necked fuse segments to affect operation of an IC. In embodiments, the fuse structure includes a pair of neighboring interconnect lines equidistant from a center interconnect line. In further embodiments, the center interconnect line, and at least one of the neighboring interconnect lines, include line segments of lateral widths that differ by a same, and complementary amount. In further embodiments, the center interconnect line is interconnected at opposite ends of a necked line segment. In further embodiments, the necked line segment is fabricated with pitch-reducing spacer-based patterning process.Type: ApplicationFiled: May 8, 2014Publication date: January 19, 2017Inventors: Zhanping Chen, Andrew W. Yeoh, Seongtae Jeong, Uddalak Bhattacharya, Charles H. Wallace
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Patent number: 9123724Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.Type: GrantFiled: December 19, 2013Date of Patent: September 1, 2015Assignee: Intel CorporationInventors: Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
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Publication number: 20140103448Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.Type: ApplicationFiled: December 19, 2013Publication date: April 17, 2014Inventors: Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
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Patent number: 8618613Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.Type: GrantFiled: March 31, 2011Date of Patent: December 31, 2013Assignee: Intel CorporationInventors: Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
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Patent number: 8411482Abstract: A memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion of the stack couples the program voltage to a terminal of the transistor in a cell. A second portion of the stack couples the program voltage to a terminal of the transistor in another cell.Type: GrantFiled: August 20, 2008Date of Patent: April 2, 2013Assignee: Intel CorporationInventors: Zhanping Chen, Sarvesh Kulkarni, Kevin Zhang
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Patent number: 8395923Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.Type: GrantFiled: December 16, 2009Date of Patent: March 12, 2013Assignee: Intel CorporationInventors: Zhanping Chen, Sarvesh H. Kulkarni, Kevin Zhang
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Patent number: 8331186Abstract: A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession.Type: GrantFiled: January 7, 2011Date of Patent: December 11, 2012Assignee: Intel CorporationInventors: Jun He, Zhanping Chen, Jeffrey Hicks, Gregory F. Taylor
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Publication number: 20120248546Abstract: Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Inventors: Xianghong Tong, Zhanping Chen, Walid M. Hafez, Zhiyong Ma, Sarvesh H. Kulkarni, Kevin X. Zhang, Matthew B. Pedersen, Kevin D. Johnson
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Patent number: 8242831Abstract: A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.Type: GrantFiled: December 31, 2009Date of Patent: August 14, 2012Assignee: Intel CorporationInventors: Xianghong Tong, Zhanping Chen, Kevin X. Zhang, Zhiyong Ma, Kevin D. Johnson, Jun He
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Patent number: 8101471Abstract: A programmable anti-fuse element includes a substrate (224), an N-well (426) in the substrate, an electrically insulating layer (427) over the N-well, and a gate electrode (430) over the electrically insulating layer. The gate electrode has n-type doping so that the N-well is able to substantially contain within its boundaries a current generated following a programming event of the programmable anti-fuse element. In the same or another embodiment, a twice-programmable fuse element (100) includes a metal gate fuse (110) and an oxide anti-fuse (120) such as the programmable anti-fuse element just described.Type: GrantFiled: December 30, 2008Date of Patent: January 24, 2012Assignee: Intel CorporationInventors: Walid M. Hafez, Chia-Hong Jan, Jie-Feng Lin, Chetan Prasad, Sangwoo Pae, Zhanping Chen, Anisur Rahman
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Publication number: 20110156801Abstract: A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Inventors: Xianghong Tong, Zhanping Chen, Kevin X. Zhang, Zhiyong Ma, Kevin D. Johnson, Jun He
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Publication number: 20110103170Abstract: An embodiment of the present invention is a technique to program a fuse. A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession.Type: ApplicationFiled: January 7, 2011Publication date: May 5, 2011Applicant: INTEL CORPORATIONInventors: Jun He, Zhanping Chen, Jeffrey Hicks, Gregory F. Taylor
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Patent number: 7924596Abstract: A programmable ROM (PROM) architecture includes cascode NMOS transistors with a fuse bit cell that is arrayed, with sleep transistors located in each column of the array that in a standby mode shut down the entire fuse array. A fuse redundancy scheme may be used to repair a defective fuse row.Type: GrantFiled: September 26, 2007Date of Patent: April 12, 2011Assignee: Intel CorporationInventors: Zhanping Chen, Kevin Zhang
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Patent number: 7889587Abstract: A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession.Type: GrantFiled: December 6, 2006Date of Patent: February 15, 2011Assignee: Intel CorporationInventors: Jun He, Zhanping Chen, Jeffrey Hicks, Gregory F. Taylor