Patents by Inventor Zhao-Cheng Chen

Zhao-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240015879
    Abstract: A plasma device includes a hollow chamber casing, at least one hollow electrode tube, and an intermediate frequency plasma power supply. The hollow chamber casing has a chamber. The at least one hollow electrode tube is disposed within the chamber, in which a tube wall of the at least one hollow electrode tube is provided with several holes. The intermediate frequency plasma power supply has a first potential terminal and a second potential terminal. The first potential terminal and the second potential terminal have different potentials. The first potential terminal and the second potential terminal are respectively connected to the hollow chamber casing and the at least one hollow electrode tube.
    Type: Application
    Filed: March 21, 2023
    Publication date: January 11, 2024
    Inventors: Yu Chi CHANG, Zhao-Cheng CHEN
  • Publication number: 20240011157
    Abstract: A deposition apparatus includes a chamber, a susceptor, several injection pipes, and a plasma device. The susceptor is disposed within the chamber and is configured to carry a substrate. The injection pipes are respectively disposed in and pass through an upper portion of the chamber and are located over the susceptor. A nozzle of each of the injection pipes is tangent to an inner side surface of the chamber, so that several process gases ejected through the nozzles of the injection pipes respectively rotate along the inner side surface of the chamber. The process gases at least include a precursor gas. The plasma device is disposed in and passes through a top of the chamber, and is configured to generate plasma within the chamber to activate the precursor gas to form activators.
    Type: Application
    Filed: February 23, 2023
    Publication date: January 11, 2024
    Inventors: Yu Chi CHANG, Zhao-Cheng CHEN
  • Patent number: 11688787
    Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • Publication number: 20210226029
    Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventors: Yu-Lien HUANG, Chi-Wen LIU, Clement Hsingjen WANN, Ming-Huan TSAI, Zhao-Cheng CHEN
  • Patent number: 10971594
    Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • Publication number: 20200013869
    Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Inventors: Yu-Lien HUANG, Chi-Wen LIU, Clement Hsingjen WANN, Ming-Huan TSAI, Zhao-Cheng CHEN
  • Patent number: 10515945
    Abstract: A semiconductor device includes a first conductive structure directly over an isolation structure; a second conductive structure directly over an active region; a first dielectric layer over the first and second conductive structures; a second dielectric layer over the first dielectric layer, wherein the first and second dielectric layers include different materials; a first conductive feature contacting the first conductive structure through at least the first and second dielectric layers; and a second conductive feature contacting the second conductive structure through at least the first and second dielectric layers, wherein the first and second conductive features include a same metal.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Patent number: 10418456
    Abstract: A method of forming a semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is formed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: September 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • Publication number: 20190115336
    Abstract: A semiconductor device includes a first conductive structure directly over an isolation structure; a second conductive structure directly over an active region; a first dielectric layer over the first and second conductive structures; a second dielectric layer over the first dielectric layer, wherein the first and second dielectric layers include different materials; a first conductive feature contacting the first conductive structure through at least the first and second dielectric layers; and a second conductive feature contacting the second conductive structure through at least the first and second dielectric layers, wherein the first and second conductive features include a same metal.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 18, 2019
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Patent number: 10163887
    Abstract: A semiconductor device includes a first gate stack over an insulator, a second gate stack over an active region, a first dielectric layer over the first and second gate stacks, a second dielectric layer over the first dielectric layer, and a metal layer over the first and second gate stacks. The first and second dielectric layers include different materials. The metal layer contacts the second gate stack by penetrating at least the first and second dielectric layers and is isolated from the first gate stack by at least the first and second dielectric layers.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Patent number: 10134897
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a surface of the substrate. A recess cavity is formed in the substrate adjacent to the gate stack. A first epitaxial (epi) material is then formed in the recess cavity. A second epi material is formed over the first epi material. A portion of the second epi material is removed by a removing process. The disclosed method provides an improved method by providing a second epi material and the removing process for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Zhao-Cheng Chen
  • Publication number: 20180240790
    Abstract: A semiconductor device includes a first gate stack over an insulator, a second gate stack over an active region, a first dielectric layer over the first and second gate stacks, a second dielectric layer over the first dielectric layer, and a metal layer over the first and second gate stacks. The first and second dielectric layers include different materials. The metal layer contacts the second gate stack by penetrating at least the first and second dielectric layers and is isolated from the first gate stack by at least the first and second dielectric layers.
    Type: Application
    Filed: April 13, 2018
    Publication date: August 23, 2018
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Patent number: 9947646
    Abstract: A semiconductor device includes a substrate having first and second regions. The first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The semiconductor device further includes first and second gate stacks over the insulator; a third gate stack over the channel region; a first dielectric layer over the first, second, and third gate stacks; a second dielectric layer over the first dielectric layer; and a metal layer over the first and second gate stacks. The metal layer is in electrical communication with the second gate stack and is isolated from the first gate stack by at least the first and second dielectric layers.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Publication number: 20170271469
    Abstract: A method of forming a semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is formed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Yu-Lien Huang, Chi-Wen LIU, Clement Hsingjen WANN, Ming-Huan TSAI, Zhao-Cheng CHEN
  • Publication number: 20170229440
    Abstract: A semiconductor device includes a substrate having first and second regions. The first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The semiconductor device further includes first and second gate stacks over the insulator; a third gate stack over the channel region; a first dielectric layer over the first, second, and third gate stacks; a second dielectric layer over the first dielectric layer; and a metal layer over the first and second gate stacks. The metal layer is in electrical communication with the second gate stack and is isolated from the first gate stack by at least the first and second dielectric layers.
    Type: Application
    Filed: April 21, 2017
    Publication date: August 10, 2017
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Patent number: 9673292
    Abstract: A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • Publication number: 20170141104
    Abstract: A method of forming a semiconductor device provides a precursor that includes a substrate having first and second regions, wherein the first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The precursor further includes gate stacks over the insulator, and gate stacks over the channel regions. The precursor further includes a first dielectric layer over the gate stacks. The method further includes partially recessing the first dielectric layer; forming a second dielectric layer over the recessed first dielectric layer; and forming a contact etch stop (CES) layer over the second dielectric layer. In an embodiment, the method further includes forming gate via holes over the gate stacks, forming source and drain (S/D) via holes over the S/D regions, and forming vias in the gate via holes and S/D via holes.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Patent number: 9633999
    Abstract: A method of forming a semiconductor device provides a precursor that includes a substrate having first and second regions, wherein the first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The precursor further includes gate stacks over the insulator, and gate stacks over the channel regions. The precursor further includes a first dielectric layer over the gate stacks. The method further includes partially recessing the first dielectric layer; forming a second dielectric layer over the recessed first dielectric layer; and forming a contact etch stop (CES) layer over the second dielectric layer. In an embodiment, the method further includes forming gate via holes over the gate stacks, forming source and drain (S/D) via holes over the S/D regions, and forming vias in the gate via holes and S/D via holes.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Publication number: 20160079383
    Abstract: A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.
    Type: Application
    Filed: November 25, 2015
    Publication date: March 17, 2016
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • Publication number: 20160043224
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a surface of the substrate. A recess cavity is formed in the substrate adjacent to the gate stack. A first epitaxial (epi) material is then formed in the recess cavity. A second epi material is formed over the first epi material. A portion of the second epi material is removed by a removing process. The disclosed method provides an improved method by providing a second epi material and the removing process for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.
    Type: Application
    Filed: October 20, 2015
    Publication date: February 11, 2016
    Inventors: Yu-Lien Huang, Zhao-Cheng Chen