Patents by Inventor Zhao Lun
Zhao Lun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220207686Abstract: A system for inspecting an object for defects includes a component inspecting module (4) and an inspecting module (7). The system executes the following steps: identifying at least one component (400) and detecting defects of the identified component (400) through comparing one or more characteristics of at least one element of the component (400) with those of a specimen, wherein the components (400) of the object, upon being identified, are each assigned a corresponding inspection algorithm (307) by an assigning module (6) based on an inspection criteria for the object to be inspected.Type: ApplicationFiled: December 29, 2021Publication date: June 30, 2022Inventors: SHIN JIE WONG, HM FAZLE RABBI, JUNE WAI YAP, ZHAO HONG LIM, ZHAO LUN LEE
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Patent number: 9431528Abstract: A lithographic stack over a raised structure (e.g., fin) of a non-planar semiconductor structure, such as a FinFET, includes a bottom layer of spin-on amorphous carbon or spin-on organic planarizing material, a hard mask layer of a nitride and/or an oxide on the spin-on layer, a layer of a developable bottom anti-reflective coating (dBARC) on the hard mask layer, and a top layer of photoresist. The stack is etched to expose and recess the raised structure, and epitaxial structure(s) are grown on the recess.Type: GrantFiled: May 19, 2014Date of Patent: August 30, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Hong Yu, Xiang Hu, Zhao Lun, Huang Liu
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Patent number: 9419101Abstract: A method of forming spacers and the resulting fin-shaped field effect transistors are provided. Embodiments include forming a silicon (Si) fin over a substrate; forming a polysilicon gate over the Si fin; and forming a spacer on top and side surfaces of the polysilicon gate, and on exposed upper and side surfaces of the Si fin, the spacer including: a first layer and second layer having a first dielectric constant, and a third layer formed between the first and second layers and having a second dielectric constant, wherein the second dielectric constant is lower than the first dielectric constant.Type: GrantFiled: November 4, 2015Date of Patent: August 16, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Jianwei Peng, Hong Yu, Zhao Lun, Tao Han, Hsien-Ching Lo, Basab Banerjee, Wen Zhi Gao, Byoung-Gi Min
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Patent number: 9362176Abstract: The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures.Type: GrantFiled: June 30, 2014Date of Patent: June 7, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Hong Yu, HongLiang Shen, Zhao Lun, Zhenyu Hu, Richard J. Carter
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Patent number: 9337306Abstract: Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a first portion of the epi S/D is formed in the S/D region on a fin in a finned substrate. After the first portion is formed, but before completion of the formation of the S/D, a secondary spacer is formed in the S/D region. Then, the remainder portion of the S/D is formed in the S/D region. As a result, the S/D is separated from the gate stack by the secondary spacer.Type: GrantFiled: June 30, 2014Date of Patent: May 10, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Jianwei Peng, Xusheng Wu, Hong Yu, Zhao Lun
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Publication number: 20150380515Abstract: Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a first portion of the epi S/D is formed in the S/D region on a fin in a finned substrate. After the first portion is formed, but before completion of the formation of the S/D, a secondary spacer is formed in the S/D region. Then, the remainder portion of the S/D is formed in the S/D region. As a result, the S/D is separated from the gate stack by the secondary spacer.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Inventors: Jianwei Peng, Xusheng Wu, Hong Yu, Zhao Lun
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Publication number: 20150380316Abstract: The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Hong YU, HongLiang SHEN, Zhao LUN, Zhenyu HU, Richard J. Carter
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Publication number: 20150332934Abstract: A lithographic stack over a raised structure (e.g., fin) of a non-planar semiconductor structure, such as a FinFET, includes a bottom layer of spin-on amorphous carbon or spin-on organic planarizing material, a hard mask layer of a nitride and/or an oxide on the spin-on layer, a layer of a developable bottom anti-reflective coating (dBARC) on the hard mask layer, and a top layer of photoresist. The stack is etched to expose and recess the raised structure, and epitaxial structure(s) are grown on the recess.Type: ApplicationFiled: May 19, 2014Publication date: November 19, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Hong YU, Xiang HU, Zhao LUN, Huang LIU
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Patent number: 9059218Abstract: A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide layer and a top nitride layer are provided over the dummy gate structure and active region to protect the dummy gate during source and drain implantation. The active region is implanted using dopants such as, a n-type dopant or a p-type dopant to create a source region and a drain region in the active region, after which the sacrificial conformal layer is removed.Type: GrantFiled: September 18, 2013Date of Patent: June 16, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Bharat Krishnan, Jinping Liu, Zhao Lun, Hui Zhan, Bongki Lee
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Patent number: 8987083Abstract: In a non-planar based semiconductor process where the structure includes both N and P type raised structures (e.g., fins), and where a different type of epitaxy is to be grown on each of the N and P type raised structures, prior to the growing, a lithographic blocking material over one of the N and P type raised structure portions is selectively etched to expose and planarize a gate cap. After the first type of epitaxy is grown, the process is repeated for the other of the N and P type epitaxy.Type: GrantFiled: March 10, 2014Date of Patent: March 24, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Zhenyu Hu, Zhao Lun, Xing Zhang
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Publication number: 20150076622Abstract: A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide layer and a top nitride layer are provided over the dummy gate structure and active region to protect the dummy gate during source and drain implantation. The active region is implanted using dopants such as, a n-type dopant or a p-type dopant to create a source region and a drain region in the active region, after which the sacrificial conformal layer is removed.Type: ApplicationFiled: September 18, 2013Publication date: March 19, 2015Inventors: Bharat Krishnan, Jinping Liu, Zhao Lun, Hui Zhan, Bongki Lee
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Patent number: 8716081Abstract: A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.Type: GrantFiled: March 15, 2007Date of Patent: May 6, 2014Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Lee Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee, Shailendra Mishra, Johnny Widodo
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Patent number: 8274115Abstract: A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer.Type: GrantFiled: March 19, 2008Date of Patent: September 25, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lee Wee Teo, Chung Woh Lai, Johnny Widodo, Shyue Seng Tan, Shailendra Mishra, Zhao Lun, Yong Meng Lee, Jeffrey Chee
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Patent number: 8178417Abstract: A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.Type: GrantFiled: April 22, 2008Date of Patent: May 15, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shailendra Mishra, James Yong Meng Lee, Zhao Lun, Wen Zhi Gao, Chung Woh Lai, Huang Liu, Johnny Widodo, Liang Choo Hsia
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Patent number: 8143651Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.Type: GrantFiled: August 2, 2010Date of Patent: March 27, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Johnny Widodo, Liang Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun, Huang Liu, Chung Woh Lai, Shailendra Mishra, Yew Tuck Chow, Fang Chen, Shiang Yang Ong
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Patent number: 8053327Abstract: An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.Type: GrantFiled: December 21, 2006Date of Patent: November 8, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shailendra Mishra, Lee Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee, Johnny Widodo
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Patent number: 7999300Abstract: A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.Type: GrantFiled: January 28, 2009Date of Patent: August 16, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Zhao Lun, James Yong Meng Lee, Lee Wee Teo, Shyue Seng Tan, Chung Woh Lai, Johnny Widodo, Shailendra Mishra, Jeffrey Chee
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Patent number: 7932178Abstract: A method is provided for manufacturing an integrated circuit having a plurality of MOSFET devices, comprising the steps of: providing a plurality of MOSFET devices each having a first and a second structural parameter associated therewith, wherein a value of one of the first and a second structural parameter of each device is selected to provide a value of a performance parameter of the device substantially equal to a predetermined reference value, the predetermined reference value being the same for each device.Type: GrantFiled: December 28, 2006Date of Patent: April 26, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lee Wee Teo, Yong Meng Lee, Jeffrey Chee, Shyue Seng Tan, Chung Woh Lai, Johnny Widodo, Zhao Lun, Shailendra Mishra
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Publication number: 20100301424Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.Type: ApplicationFiled: August 2, 2010Publication date: December 2, 2010Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Johnny WIDODO, Liang Choo HSIA, James Yong Meng LEE, Wen Zhi GAO, Zhao LUN, Huang LIU, Chung Woh LAI, Shailendra MISHRA, Yew Tuck CHOW, Fang CHEN, Shiang Yang ONG
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Patent number: 7838390Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.Type: GrantFiled: October 12, 2007Date of Patent: November 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-jung Kim, Joo-chan Kim, Jae-eon Park, Richard Anthony Conti, Zhao Lun, Johnny Widodo, William C. Wille, Biao Zuo