Patents by Inventor Zhao Lun
Zhao Lun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7795680Abstract: An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.Type: GrantFiled: December 7, 2007Date of Patent: September 14, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Huang Liu, Alex K. H. See, James Lee, Johnny Widodo, Chung Woh Lai, Wenzhi Gao, Zhao Lun, Shailendra Mishra, Liang-Choo Hsia
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Patent number: 7767577Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.Type: GrantFiled: February 14, 2008Date of Patent: August 3, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Johnny Widodo, Liang Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun, Huang Liu, Chung Woh Lai, Shailendra Mishra, Yew Tuck Chow, Fang Chen, Shiang Yang Ong
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Publication number: 20100187587Abstract: A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.Type: ApplicationFiled: January 28, 2009Publication date: July 29, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Zhao LUN, James Yong Meng LEE, Lee Wee TEO, Shyue Seng TAN, Chung Woh LAI, Johnny WIDODO, Shailendra MISHRA, Jeffrey CHEE
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Publication number: 20100009527Abstract: A method for manufacturing an integrated circuit system that includes: providing a substrate; forming a mask layer over the substrate; implanting a first well through an opening in the mask layer into the substrate; and implanting a second well through the mask layer and the opening via a single implant into the substrate.Type: ApplicationFiled: July 14, 2008Publication date: January 14, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Yong Meng Lee, Chung Woh Lai, Huang Liu, Wenzhi Gao, Zhao Lun, Johnny Widodo, Shailendra Mishra, Liang-Choo Hsia
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Publication number: 20090261448Abstract: A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.Type: ApplicationFiled: April 22, 2008Publication date: October 22, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Shailendra MISHRA, James Yong Meng LEE, Zhao LUN, Wen Zhi GAO, Chung Woh LAI, Huang LIU, Johnny WIDODO, Liang Choo HSIA
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Publication number: 20090236663Abstract: A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Lee Wee Teo, Chung Woh Lai, Johnny Widodo, Shyue Seng Tan, Shailendra Mishra, Zhao Lun, Yong Meng Lee, Jeffrey Chee
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Publication number: 20090206408Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Johnny WIDODO, Liang Choo HSIA, James Yong Meng LEE, Wen Zhi GAO, Zhao LUN, Huang LIU, Chung Woh LAI, Shailendra MISHRA, Yew Tuck CHOW, Fang CHEN, Shiang Yang ONG
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Publication number: 20090146262Abstract: An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.Type: ApplicationFiled: December 7, 2007Publication date: June 11, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Huang Liu, Alex K.H. See, James Lee, Johnny Widodo, Chung Woh Lai, Wenzhi Gao, Zhao Lun, Shailendra Mishra, Liang-Choo Hsia
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Publication number: 20090098706Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.Type: ApplicationFiled: October 12, 2007Publication date: April 16, 2009Inventors: Jun-jung Kim, Joo-chan Kim, Jae-eon Park, Richard Anthony Conti, Zhao Lun, Johnny Widodo, William C. Wille, Biao Zuo
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Patent number: 7485524Abstract: The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate. The surface recesses preferable each has a bottom surface that is parallel to the substrate surface, which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces can be readily formed by crystallographic etching of the semiconductor substrate, followed by epitaxial growth of a semiconductor material.Type: GrantFiled: June 21, 2006Date of Patent: February 3, 2009Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.Inventors: Zhijiong Luo, Yung F. Chong, Judson R. Holt, Zhao Lun, Huilong Zhu
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Publication number: 20080224228Abstract: A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.Type: ApplicationFiled: March 15, 2007Publication date: September 18, 2008Inventors: Lee Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee, Shailendra Mishra, Johnny Widodo
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Publication number: 20080157223Abstract: A method is provided for manufacturing an integrated circuit having a plurality of MOSFET devices, comprising the steps of: providing a plurality of MOSFET devices each having a first and a second structural parameter associated therewith, wherein a value of one of the first and a second structural parameter of each device is selected to provide a value of a performance parameter of the device substantially equal to a predetermined reference value, the predetermined reference value being the same for each device.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Lee Wee Teo, Yong Meng Lee, Jeffrey Chee, Shyue Seng Tan, Chung Woh Lai, Johnny Widodo, Zhao Lun, Shailendra Mishra
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Publication number: 20080150074Abstract: An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Shailendra Mishra, Lee Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee, Johnny Widodo
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Publication number: 20080087958Abstract: A semiconductor device provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.Type: ApplicationFiled: December 6, 2007Publication date: April 17, 2008Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Purakh Verma, Liang-Choo Hsia, Dong Kyun Sohn, Guowei Zhang, Chew Hoe Ang, Yun Ling Tan, Zhao Lun, Jae Gon Lee, Yung Fu Chong
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Patent number: 7326609Abstract: A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.Type: GrantFiled: May 6, 2005Date of Patent: February 5, 2008Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Purakh Raj Verma, Liang-Choo Hsia, Dong Kyun Sohn, Guowei Zhang, Chew Hoe Ang, Yun Ling Tan, Zhao Lun, Jae Gon Lee, Yung Fu Chong
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Publication number: 20080006854Abstract: The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate. The surface recesses preferable each has a bottom surface that is parallel to the substrate surface, which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces can be readily formed by crystallographic etching of the semiconductor substrate, followed by epitaxial growth of a semiconductor material.Type: ApplicationFiled: June 21, 2006Publication date: January 10, 2008Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CHARTERED SEMICONDUCTOR MANUFACTURING LTDInventors: Zhijiong Luo, Yung F. Chong, Judson R. Holt, Zhao Lun, Huilong Zhu
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Publication number: 20070293016Abstract: A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.Type: ApplicationFiled: June 14, 2006Publication date: December 20, 2007Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CHARTERED SEMICONDUCTOR MANUFACTURING LTD., INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventors: Zhijiong Luo, Hung Y. Ng, Nivo Rovedo, Phung T. Nguyen, William C. Wille, Richard Lindsay, Zhao Lun, Yung Fu Chong, Siddhartha Panda
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Patent number: 7259072Abstract: A method is described to fabricate a MOSFET device with increased threshold voltage stability. After the pad oxide and pad nitride are deposited on the silicon substrate and shallow trenches are patterned and the pad nitride removed. As+ or P+ species are then implanted using low energy ions of approximately 5 keV into the pad oxide. Conventional As+ or P+ implant follows the shallow implant to form the n-wells. With this procedure of forming a sacrificial shallow implantation oxide layer, surface dopant concentration variation at pad oxide:silicon substrate interface is minimized; and threshold voltage stability variation of the device is significantly decreased.Type: GrantFiled: April 21, 2004Date of Patent: August 21, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yisuo Li, Francis Benistant, Kim Hyun Sik, Zhao Lun
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Publication number: 20060252188Abstract: A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.Type: ApplicationFiled: May 6, 2005Publication date: November 9, 2006Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Purakh Verma, Liang-Choo Hsia, Dong Kyun Sohn, Guowei Zhang, Chew Hoe Ang, Yun Ling Tan, Zhao Lun, Jae Gon Lee, Yung Fu Chong
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Patent number: 6998682Abstract: A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific locations of the MOSFET device structure for purposes of reducing the risk of parasitic transistor formation underlying a gate structure junction. After formation of either a “T” shaped, or an “H” shaped gate structure, body contact regions of a first conductivity type are formed adjacent to both an STI region and to a component of the gate structure. Formation of a source/drain region of a second conductivity type located on the opposite side of the same STI region, and the same gate structure component, is next performed. Unwanted parasitic transistor formation, which can occur underlying the gate structure via the body contact region and the source/drain region, is prevented by the presence of the separating STI region.Type: GrantFiled: May 12, 2005Date of Patent: February 14, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yeen Tat Chan, Kheng Chok Tee, Yiang Aun Nga, Zhao Lun, Wang Ling Goh, Diing Shenp Ang