Patents by Inventor Zhen Zhou

Zhen Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260203365
    Abstract: A Method for performing a target transformation by using acceleration hardware is provided. The transformation operation of the ith stage includes: respectively reading a first data pair and a second data pair from first and second read addresses in the memory at an (i?1)th stage; performing a first rearrangement operation on the first and second data pairs, to output a third data pair and a fourth data pair; performing a radix-2 butterfly operation on the third data pair and the fourth data pair, to output a first result pair and a second result pair; performing a second rearrangement operation on the first result pair and the second result pair, to obtain a fifth data pair and a sixth data pair; and respectively writing the fifth and sixth data pairs into first and second write addresses in the memory at the ith stage.
    Type: Application
    Filed: January 9, 2026
    Publication date: July 16, 2026
    Inventors: Zhen Zhou, Xin TANG, Chen YANG, Zihang WANG, Jianfei WANG
  • Patent number: 12642132
    Abstract: Embodiments of a microelectronic assembly comprise a package substrate, a first integrated circuit (IC) die, a second IC die between the first IC die and the package substrate, a dielectric material between the first IC die and the package substrate, and a plurality of vias through the dielectric material, the vias coupling the first IC die and the package substrate. The microelectronic assembly is in a space defined by three mutually orthogonal axes, a first axis, a second axis and a third axis; the package substrate, the first IC die and the second IC die are mutually parallel in first planes defined by the first axis and the third axis; the vias are in one or more second planes defined by the second axis and the third axis; and the vias are inclined at an angle not equal to ninety degrees around the first axis.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: May 26, 2026
    Assignee: Intel Corporation
    Inventors: Jong-Ru Guo, Zhen Zhou, Jason Mix, Chia-Pin Chiu, Zuoguo Wu
  • Patent number: 12631897
    Abstract: A naked-eye three-dimensional (3D) display device is provided. The naked-eye 3D display device comprises: a display component, comprising an array of display units; and a viewing angle regulator, comprising an array of microprism blocks. The microprism blocks are divided into a plurality of groups, and an angle combination of a first angle and a second angle of each of the microprism blocks is preset so that outgoing lights of the same group of microprism blocks converge into the same viewpoint, and outgoing lights of different groups of microprism blocks converge into different viewpoints. Hence, a plurality of different viewpoints are formed by setting angles of inclined surfaces of the microprism blocks, thereby seeing different 3D display effects from different viewing angles.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: May 19, 2026
    Assignees: SVG TECH GROUP CO., LTD, Soochow University
    Inventors: Wen Qiao, Linsen Chen, Jianyu Hua, Jiacheng Shi, Ruibin Li, Zhen Zhou, Minghui Luo, Donglin Pu, Pengfei Zhu, Tangdong Cheng
  • Patent number: 12625011
    Abstract: The present application provides a temperature detection system and an on board charger, the system including a heat transfer element and a temperature sensor; the heat transfer element and the temperature sensor are both located on a printed circuit board. The heat transfer element is thermally connected to the temperature sensor, and is also configured to thermally connect to the power device on the printed circuit board. The heat transfer element is configured to transfer a temperature of the power device to the temperature sensor, so that the temperature sensor detects the temperature of the power device. The heat transfer element is an electrically insulating element. The heat transfer element is thermally connected to the power device and temperature sensor.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: May 12, 2026
    Assignee: Delta Electronics (Shanghai) Co., Ltd.
    Inventors: Zhen Zhou, Peiai You, Jianhong Chen
  • Publication number: 20260119028
    Abstract: This application provides a handwriting elimination apparatus includes a trigger component and a strain component, and can be used in the electronic stylus pen. In this case, in a process in which an elimination action is performed on an image on the touch screen by using the handwriting elimination apparatus, a press portion transfers a force received due to contact between a trigger portion and the touch screen to a strain sensing assembly, and the strain sensing assembly undergoes deformation under a press force and generates an erasure signal corresponding to the deformation. When the force received due to the contact between the trigger portion and the touch screen changes, a deformation degree of the strain sensing assembly also changes correspondingly, and a corresponding erasure signal is generated. Different contact forces between the trigger portion and the touch screen enable the strain sensing assembly to generate different erasure signals.
    Type: Application
    Filed: December 22, 2025
    Publication date: April 30, 2026
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hu Chao, Zhen Zhou, Shuang Deng, Kun Feng
  • Publication number: 20260123380
    Abstract: A device may include a plurality of chiplets stacked on top of each other. Each chiplet includes a central region and an edge region outside the central region; one or more electronic components disposed within the central region; and a plurality of through-chiplet vias extending through the chiplet. The plurality of through-chiplet vias are disposed in the edge region. The device may further include a coil including a plurality of turns formed in at least two chiplets of the plurality of chiplets. Each turn includes at least two through-chiplet vias of at least one chiplet of the plurality of chiplets. The through-chiplet vias of the plurality of through-chiplet vias of the at least two turns of the plurality of turns of the coil are formed in a common plane perpendicular to main surfaces of the plurality of chiplets.
    Type: Application
    Filed: December 24, 2025
    Publication date: April 30, 2026
    Inventors: Terry William GILMORE, Zhen ZHOU
  • Patent number: 12614844
    Abstract: Photonically steered impedance surface antennas are disclosed. A disclosed example apparatus includes a semiconductor substrate to be communicatively coupled to a radio frequency (RF) source, an at least partially transparent dielectric layer, the semiconductor substrate at a first side of the at least partially transparent dielectric layer, an at least partially transparent conductive film at a second side of the at least partially transparent dielectric layer that is opposite the first side of the at least partially transparent dielectric layer, and an illumination source to illuminate at least a portion of the semiconductor substrate to generate a photoinduced solid-state plasma pattern that beam steers an RF signal corresponding to the RF source.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: April 28, 2026
    Assignee: Intel Corporation
    Inventors: Zhen Zhou, Tae Young Yang, Timo Huusari, Renzhi Liu, Wei Qian, Mengyuan Huang, Jason Mix
  • Publication number: 20260093658
    Abstract: A host system, a device system, a data transfer method, a storage medium, and a computer program product are provided. The data transfer method includes: initiating, by a host controller, a data transfer transaction, where each data transfer transaction includes a start-of-frame packet indicating a beginning of the data transfer transaction, a USB standard-based protocol interval exists between two adjacent start-of-frame packets, and when the host controller sends a plurality of data transfer transactions, an interval between two adjacent start-of-frame packets is less than the protocol interval; and performing a physical connection between a host physical layer and a device physical layer to implement a data transfer, where the data transfer has a USB standard-based protocol symbol rate, and during the physical connection, a symbol rate of the data transfer is greater than the protocol symbol rate. The present invention improves USB data transfer efficiency.
    Type: Application
    Filed: September 25, 2025
    Publication date: April 2, 2026
    Inventors: Jinghua Hu, Ming Shi, Yong Zhang, Hui Xu, Wei Zhong, Zhen Zhou
  • Patent number: 12592508
    Abstract: In one embodiment, an interconnect apparatus (e.g., an interposer apparatus) includes a plurality of interconnect probes that each include a wave spring structure that includes a plurality of stacked wave spring discs. The wave spring discs may be formed in a sinusoidal wave form shape, or in another wave form shape.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: March 31, 2026
    Assignee: Intel Corporation
    Inventors: Ismael Franco Núñez, Daqiao Du, Zhen Zhou, Gordon P. Melz
  • Publication number: 20260076265
    Abstract: A device may include a first die, including: a data transmission interface configured to inductively transmit and receive signals; a processor configured to generate a transmission asynchronous pattern; receive a response pattern via the data transmission interface indicating whether the transmission asynchronous pattern was received by a second die; control a data transfer between the first die and the second die via the data transmission interface based on the response pattern; and a second die, including: a data transmission interface configured to inductively transmit and receive signals; a processor configured to receive the transmission asynchronous pattern; check whether the received transmission asynchronous pattern is correct; generate a response pattern indicating whether the received transmission asynchronous pattern is correct; control a data transfer between the first die and the second die via the data transmission interface based on the check whether the received transmission asynchronous patte
    Type: Application
    Filed: November 14, 2025
    Publication date: March 12, 2026
    Inventors: Shamsul ABEDIN, Dekang CHEN, Stephen MOREIN, Tina C. TOUPAL, Zhen ZHOU
  • Publication number: 20260052975
    Abstract: Disclosed herein are devices, systems, and methods related to edge couplers for providing wireless channel interconnects between edges of chiplets, components, modules, devices, packages, SoCs, etc. Such edge couplers may be formed from a stack of multiple layers and a core arranged between layers of the stack. A driven via extends from at least one feed layer of the stack of multiple layers into the core, wherein the driven via is isolated from ground. A plurality of grounded through-hole vias are grounded, extend from at least one ground layer of the stack, and traverse through the core, wherein the plurality of grounded through-hole vias partially surround the driven via.
    Type: Application
    Filed: July 11, 2025
    Publication date: February 19, 2026
    Inventors: Tae Young YANG, Shuhei YAMADA, Tolga ACIKALIN, Zhen ZHOU, Kenneth P. FOUST, Bryce D. HORINE, Harry SKINNER
  • Patent number: 12548705
    Abstract: An integrated voltage regulator comprises a plurality of semiconductor devices and a circuit board including a plurality of thermally conductive inlays. At least one of the plurality of electronic devices is thermally coupled to at least one of the plurality of thermally conductive inlays. A substrate is thermally coupled to the circuit board and to the plurality of thermally conductive inlays.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: February 10, 2026
    Assignee: Navitas Semiconductor Limited
    Inventors: Hao Sun, Zhen Zhou
  • Publication number: 20260036983
    Abstract: A method and device for operation planning of a movable platform, and a storage medium are provided. The method includes: obtaining a three-dimensional model of an operation area of a movable platform; controlling a motion trajectory of a virtual movable platform in the three-dimensional model based on a detected motion control operation; determining multiple target position points on the motion trajectory based on a detected position confirmation operation, where the multiple target position points are used to generate an operation path of the movable platform in the operation area. By simulating the control of the movable platform in the real world, controlling the motion trajectory of the virtual movable platform in the three-dimensional model of the operation area, and thereby determining target position points, the operation path determined using this method is safer, more reasonable, and has higher accuracy.
    Type: Application
    Filed: October 13, 2025
    Publication date: February 5, 2026
    Applicant: SZ DJI TECHNOLOGY CO., LTD.
    Inventors: Hengbin FANG, Chen CHEN, Zhen ZHOU
  • Publication number: 20260040969
    Abstract: Various aspects relate to electronic memory devices and mechanisms for communicating with electronic memory devices. A plurality of stacked semiconductor wafers forms a wafer stack. A logic base die is configured to support the plurality of stacked semiconductor wafers. At least one through silicon via is formed through the plurality of stacked semiconductor wafers, wherein the at least one through silicon via is configured to form an inductive coil that is configured to provide a communication interface to the plurality of stacked semiconductor wafers.
    Type: Application
    Filed: October 15, 2025
    Publication date: February 5, 2026
    Inventors: Shamsul ABEDIN, Stephen MOREIN, Tina C. TOUPAL, Zhen ZHOU
  • Patent number: 12527962
    Abstract: Disclosed in the present invention is a pacing device for preventing occurrence of atrial fibrillation following premature atrial contraction, including: adjusting values of the number M of atrial events and the number N of premature atrial contraction events to control a pacing control process for preventing the occurrence of atrial fibrillation following premature atrial contraction to take place after a single or more than one premature atrial contraction events, and on the basis of a current p-p? interval, an atrial safe pacing interval and an average atrial interval, setting a smooth transition pacing sequence. The smooth transition pacing sequence avoids atrial compensation intervals caused by the premature atrial contraction and avoids occurrence of a “short-long-short” sequence.
    Type: Grant
    Filed: April 4, 2023
    Date of Patent: January 20, 2026
    Assignee: CORERHYTHM MEDICAL TECHNOLOGY (HANGZHOU) CO., LTD.
    Inventors: Lian Jin, Min Huang, Guiling Li, Jianfei Wang, Zhen Zhou, Jianqu Xiong
  • Publication number: 20260005725
    Abstract: An integrated circuit device including: a plurality of integrated circuit dies, wherein each integrated circuit die of the plurality of integrated circuit dies is configured to receive or transmit a respective baseband signal; and a further integrated circuit die including: a plurality of front-end circuits, wherein each front-end circuit of the plurality of front-end circuits is coupled to a respective integrated circuit die of the plurality of integrated circuit dies.
    Type: Application
    Filed: June 28, 2024
    Publication date: January 1, 2026
    Inventors: Shuhei YAMADA, Tae Young YANG, Zhen ZHOU, Tolga ACIKALIN, Kenneth P. FOUST, Bryce D. HORINE
  • Publication number: 20260005164
    Abstract: Disclosed herein are devices, systems, and methods for driving inductive links in a memory such as a z-axis memory. The memory includes a first memory cell connected via a first inductive link comprising a first pair of double coils and a second memory cell connected via a second inductive link comprising a second pair of double coils. The first inductive link is arranged adjacent to the second inductive link. A driver circuit is configured to simultaneously drive the first and second pair of double coils with a drive current to read or write the first and second memory cells using the first and second inductive links.
    Type: Application
    Filed: June 28, 2024
    Publication date: January 1, 2026
    Inventors: Stefano PELLERANO, Zhen ZHOU, Renzhi LIU, Tae Young YANG, Richard DORRANCE, Shuhei YAMADA, Kenneth P. FOUST, Stephen MOREIN
  • Patent number: 12510971
    Abstract: Techniques for radiofrequency (RF) touch and gesture recognition are disclosed. In the illustrative embodiment, RF transmitters and receivers are connected to data lines and gate lines of a display. RF signals sent on one data or gate line may be scattered to a different data or gate line based on the presence of a nearby object, such as a finger. The amount of scattering on different data or gate lines can be used to determine a location of one or more objects.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: December 30, 2025
    Assignee: Intel Corporation
    Inventors: Hao Luo, Somnath Kundu, Brent Carlton, Zhen Zhou
  • Publication number: 20250392033
    Abstract: An integrated chiplet system includes a printed circuit board (PCB), including a first antenna; a first chiplet, electrically conductively coupled to a second antenna; a second chiplet, electrically conductively coupled to a third antenna; and a waveguide, configured to direct a signal from the first antenna to the second antenna or the third antenna.
    Type: Application
    Filed: June 25, 2024
    Publication date: December 25, 2025
    Inventors: Tae Young YANG, Woorim SHIN, Zhen ZHOU, Bryce D. HORINE
  • Patent number: 12506269
    Abstract: Various embodiments provide systems, devices, and methods for an antenna assembly included in an integrated circuit (IC) package. The antenna assembly may be used for near field wireless communication such as package-to-package and/or chip-to-chip communication. The antenna assembly may include a feed plate (e.g., a top feed) that is capacitively coupled to a first via and a second via. The feed plate may further be capacitively coupled to a loading structure. The first via may be conductively coupled to a ground potential. In some embodiments, the antenna assembly may further include a stub structure (e.g., an open stub or a short stub) that is conductively coupled to the second via. An impedance matching network may be coupled between the feed plate and an IC die that communicates using the antenna assembly. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: December 23, 2025
    Assignee: Intel Corporation
    Inventors: Zhen Zhou, Tae Young Yang, Shuhei Yamada, Tolga Acikalin, Johanny Escobar Pelaez, Kenneth Foust, Jason Mix, Renzhi Liu