Abstract: A semiconductor device comprises a drift region (100), a body region (110), a first doped region (111) and a second doped region (112)); a first trench penetrates the first doped region (111), the body region (110) extends into the drift region (100); an extension region (150) having an opposite conductivity type to the drift region (100) and surrounding the bottom wall of the first trench; where the first trench is filled with a first conductive structure (141) and a second conductive structure (142); a dielectric layer (130) formed between the second conductive structure (142) and the inner wall of the first trench, as well as between the first conductive structure (141) and the inner wall of the first trench; a second trench penetrating the first doped region (111) and the body region (110), and a dielectric layer (130) located between the third conductive structure (143) and the second trench (122).

Abstract: A preparation method for semiconductor device, comprising: forming a body region (110) in the drift region (100), forming a first doped region (111) and a second doped region (112) in the body region (110); forming a first trench (171) penetrating the first doped region (111) and the body region (110) and extending to the drift region (100); forming an extension region (150) with a conductivity type opposite to that of the drift region (100) and surrounding the bottom wall of the first trench (171); filling the first trench (171) with a dielectric layer (130) formed on the sidewall of the trench, a first conductive structure (141) located at the bottom of the trench and a second conductive structure (142) located at the top of the trench; forming a second trench (172) penetrating the body region (110) and extending into the drift region (100); filling the second trench (172) with a third conductive structure (143) and a dielectric layer (130) formed on the inner wall of the trench.

Abstract: A semiconductor device comprises a drift region (100), a body region (110), a first doped region (111) and a second doped region (112)); a first trench penetrates the first doped region (111), the body region (110) extends into the drift region (100); an extension region (150) having an opposite conductivity type to the drift region (100) and surrounding the bottom wall of the first trench; where the first trench is filled with a first conductive structure (141) and a second conductive structure (142); a dielectric layer (130) formed between the second conductive structure (142) and the inner wall of the first trench, as well as between the first conductive structure (141) and the inner wall of the first trench; a second trench penetrating the first doped region (111) and the body region (110), and a dielectric layer (130) located between the third conductive structure (143) and the second trench (122).

Abstract: A preparation method for semiconductor device, comprising: forming a body region (110) in the drift region (100), forming a first doped region (111) and a second doped region (112) in the body region (110); forming a first trench (171) penetrating the first doped region (111) and the body region (110) and extending to the drift region (100); forming an extension region (150) with a conductivity type opposite to that of the drift region (100) and surrounding the bottom wall of the first trench (171); filling the first trench (171) with a dielectric layer (130) formed on the sidewall of the trench, a first conductive structure (141) located at the bottom of the trench and a second conductive structure (142) located at the top of the trench; forming a second trench (172) penetrating the body region (110) and extending into the drift region (100); filling the second trench (172) with a third conductive structure (143) and a dielectric layer (130) formed on the inner wall of the trench.

Abstract: A VDMOS device and a manufacturing method therefor.

Abstract: The present application relates to a semiconductor device, comprising a substrate, with a body region being formed on the substrate, and a well region being formed in the body region; and further comprising trenches penetrating through the well region and the body region and extending to the substrate, wherein a first polysilicon body and a second polysilicon body, which are isolated from each other, are respectively formed at the bottom and the top of each trench to form a split gate structure, the trenches are filled with an inter-layer dielectric layer, a conductive plug penetrating through the inter-layer dielectric layer and extending into the first polysilicon body is formed in each trench, the conductive plug is isolated from the second polysilicon body by means of the inter-layer dielectric layer, the conductive plug is connected to a source electrode, and the second polysilicon body is connected to a gate electrode.

Abstract: A VDMOS device and a manufacturing method therefor.

Abstract: A method for manufacturing a trenched split-gate device, comprising: etching a semiconductor substrate to form a trench (120); depositing an oxide in the trench to form a floating-gate oxide layer in which the floating-gate oxide layer gradually thickens from top to bottom along a side wall of the trench, and a thickness of the floating gate oxide layer at a lower part of the side wall of the trench is the same as that of the floating gate oxide layer at a bottom of the trench; depositing polysilicon into the trench to form a floating-gate polysilicon layer (123); growing an insulation medium on an upper surface of the floating-gate polysilicon layer to form an isolation layer (124); and forming a control gate on the isolation layer in the trench.

Abstract: A VDMOS device and a manufacturing method therefor.

Abstract: A VDMOS device and a manufacturing method therefor.

Abstract: A trench gate lead-out structure comprises a substrate (10), a trench formed in the surface of the substrate (10) and a first dielectric layer (22) on the substrate (10), and also comprises a polysilicon gate (31) at the inner surface of the trench. The trench is partially filled by the polysilicon gate (31), so that a recess exists in the trench above the polysilicon gate (31). A second dielectric layer (41) is filled in the recess. The trench gate lead-out structure also comprises a metal plug (50). The metal plug (50) downwards penetrates through the first dielectric layer (22) and then is inserted between the second dielectric layer (41) and the polysilicon gate (31), and accordingly is connected to the polysilicon gate (31).

Abstract: The present disclosure provides a method and a device for inspecting a defect of a liquid crystal panel.

Abstract: A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.

Abstract: A trench gate structure and a manufacturing method therefor. The trench structure comprises a substrate (10), a trench on the surface of the substrate (10), an insulating spacer (20) on the substrate (10), a gate oxide layer (41) on the inner surface of the trench, and a polysilicon gate (40) on the gate oxide layer (41). The insulating spacer (20) abuts against the trench by means of a slope structure (21) of the insulating spacer; the polysilicon gate (40) extends onto the insulating spacer (20) along the slope structure (21) in the trench; the insulating spacer (20) comprises a polysilicon gate pull-up area (22) that is concave downwards with respect to other parts of the insulating spacer (20); the polysilicon gate (40) extending out of the trench is rested on the polysilicon gate pull-up area (22).

Abstract: The present disclosure provides a worktable for testing a liquid crystal panel. In one embodiment, the worktable for testing the liquid crystal panel includes: a table body, an upper surface of which being formed with a mounting groove in order to form a light-transmittance region; wherein, the table body is further formed with a slot that has an opening in a side surface of the table body and that is configured to mount a lower polarizer therein so that the lower polarizer at least covers the light-transmittance region. The present disclosure also provides a test apparatus including the mentioned worktable.

Abstract: A VDMOS device and a manufacturing method therefor.

Abstract: A VDMOS device and a manufacturing method therefor.

Abstract: The present disclosure provides a worktable for testing a liquid crystal panel. In one embodiment, the worktable for testing the liquid crystal panel includes: a table body, an upper surface of which being formed with a mounting groove in order to form a light-transmittance region; wherein, the table body is further formed with a slot that has an opening in a side surface of the table body and that is configured to mount a lower polarizer therein so that the lower polarizer at least covers the light-transmittance region. The present disclosure also provides a test apparatus including the mentioned worktable.

Abstract: A trench gate lead-out structure comprises a substrate (10), a trench formed in the surface of the substrate (10) and a first dielectric layer (22) on the substrate (10), and also comprises a polysilicon gate (31) at the inner surface of the trench. The trench is partially filled by the polysilicon gate (31), so that a recess exists in the trench above the polysilicon gate (31). A second dielectric layer (41) is filled in the recess. The trench gate lead-out structure also comprises a metal plug (50). The metal plug (50) downwards penetrates through the first dielectric layer (22) and then is inserted between the second dielectric layer (41) and the polysilicon gate (31), and accordingly is connected to the polysilicon gate (31).

Abstract: A trench gate structure and a manufacturing method therefor. The trench structure comprises a substrate (10), a trench on the surface of the substrate (10), an insulating spacer (20) on the substrate (10), a gate oxide layer (41) on the inner surface of the trench, and a polysilicon gate (40) on the gate oxide layer (41). The insulating spacer (20) abuts against the trench by means of a slope structure (21) of the insulating spacer; the polysilicon gate (40) extends onto the insulating spacer (20) along the slope structure (21) in the trench; the insulating spacer (20) comprises a polysilicon gate pull-up area (22) that is concave downwards with respect to other parts of the insulating spacer (20); the polysilicon gate (40) extending out of the trench is rested on the polysilicon gate pull-up area (22).