Abstract: A trench gate structure and a manufacturing method therefor. The trench structure comprises a substrate (10), a trench on the surface of the substrate (10), an insulating spacer (20) on the substrate (10), a gate oxide layer (41) on the inner surface of the trench, and a polysilicon gate (40) on the gate oxide layer (41). The insulating spacer (20) abuts against the trench by means of a slope structure (21) of the insulating spacer; the polysilicon gate (40) extends onto the insulating spacer (20) along the slope structure (21) in the trench; the insulating spacer (20) comprises a polysilicon gate pull-up area (22) that is concave downwards with respect to other parts of the insulating spacer (20); the polysilicon gate (40) extending out of the trench is rested on the polysilicon gate pull-up area (22).

Abstract: A semiconductor device, having an electro-static discharge (ESD) protection structure, comprises: a diode, connected between a gate and a source of the semiconductor device, and comprising a diode main body, and two connection portions, respectively connected to two terminals of the diode main body and respectively electrically connected to the gate and the source; and a substrate comprising two insulation pads disposed thereon and separated from each other. A surface of the substrate between the insulation pads is provided with an insulation layer. The diode main body is arranged on the insulation layer. The two connection portions are configured to extend, respectively, from either end of the diode main body to the insulation pad on the corresponding side. A dielectric layer is arranged on the diode and the two insulation pads, and a metal conduction line layer is arranged on the dielectric layer.

Abstract: The present disclosure provides a worktable for testing a liquid crystal panel. In one embodiment, the worktable for testing the liquid crystal panel includes: a table body, an upper surface of which being formed with a mounting groove in order to form a light-transmittance region; wherein, the table body is further formed with a slot that has an opening in a side surface of the table body and that is configured to mount a lower polarizer therein so that the lower polarizer at least covers the light-transmittance region. The present disclosure also provides a test apparatus including the mentioned worktable.

Abstract: A test pattern for testing a trench POLY over-etched step is provided. The test pattern is a trench (14) formed on a substrate (1); the trench (14) comprises a bottom surface and two side surfaces extending from the bottom surface; the trench (14) is formed on the substrate (1) with a preset angle of non-90° formed between the longitudinal direction (L) thereof and the longitudinal direction (X) of a wafer scribing trench. The test pattern can extend the scanning length of a step scanning equipment without changing the width of the trench.

Abstract: An alignment apparatus and an alignment detection method, which fall within a field of display technology, are disclosed herein. The alignment apparatus includes: a work table; a plurality of alignment rods provided on the work table, wherein a capacitor element is provided inside the alignment rod, and a capacitance of the capacitor element is changeable as the alignment rod deforms; and an alarm element connected to the capacitor element for giving an alarm when it receives a capacitance change value which exceeds a preset threshold value.

Abstract: The present disclosure provides a method and a device for inspecting a defect of a liquid crystal panel.

Abstract: An alignment apparatus and an alignment detection method, which fall within a field of display technology, are disclosed herein. The alignment apparatus includes: a work table; a plurality of alignment rods provided on the work table, wherein a capacitor element is provided inside the alignment rod, and a capacitance of the capacitor element is changeable as the alignment rod deforms; and an alarm element connected to the capacitor element for giving an alarm when it receives a capacitance change value which exceeds a preset threshold value.

Abstract: There are provided an array substrate and method for manufacturing the same, a display panel and method for testing the same, and a display apparatus. The array substrate comprises a display region and at least one bond region located outside of the display region; wherein a plurality of signal lines are disposed within the display region, and a plurality of wiring terminals connected to multiple ones of the plurality of signal lines through a plurality of first lead wires are disposed within each bond region; the array substrate further comprises one or more test regions corresponding to arbitrary one or more of the at least one bond region; wherein a plurality of test terminals are disposed within each test region, and the plurality of test terminals within any one of the one or more test regions are connected with the plurality of wiring terminals within a respective one of the at least one bond region through a plurality of second lead wires.

Abstract: There are provided an array substrate and method for manufacturing the same, a display panel and method for testing the same, and a display apparatus. The array substrate comprises a display region and at least one bond region located outside of the display region; wherein a plurality of signal lines are disposed within the display region, and a plurality of wiring terminals connected to multiple ones of the plurality of signal lines through a plurality of first lead wires are disposed within each bond region; the array substrate further comprises one or more test regions corresponding to arbitrary one or more of the at least one bond region; wherein a plurality of test terminals are disposed within each test region, and the plurality of test terminals within any one of the one or more test regions are connected with the plurality of wiring terminals within a respective one of the at least one bond region through a plurality of second lead wires.

Abstract: A trench-type DMOS device includes a substrate as a public drain region, an active region and a voltage-dividing ring formed on the substrate, and a first dielectric layer formed on the substrate. Multiple trenches are located on the first dielectric layer, and the trenches extend from the surface of the first dielectric layer into the interior of the substrate. The trenches comprise at least one first trench distributed in the active region and a second trench outside the active region. A gate oxide layer is formed in the trench and polycrystalline silicon is filled to form a gate. The active region further comprises a source electrode region and a P-type heavily doped region under the source electrode region. A second dielectric layer covers the first dielectric layer and the multiple trenches. A metal layer covers the second dielectric layer to form a first electrode region and a second electrode region.

Abstract: A trench-type DMOS device and a manufacturing method thereof are provided. The DMOS device includes: a substrate (100) used as a public drain region, an active region (102) and a voltage-dividing ring (103) formed on the substrate (100), and a first dielectric layer (110) formed on the substrate (100). Multiple trenches are located on the first dielectric layer (110), and the trenches extend from the surface of the first dielectric layer (110) into the interior of the substrate (100). The trenches comprise at least one first trench (141) distributed in the active region (102) and a second trench (142) outside the active region (102). A gate oxide layer (144) is formed in the trench and polycrystalline silicon (143) is filled to form a gate. The active region (102) further comprises a source electrode region (104) and a P-type heavily doped region (105) under the source electrode region (104). A second dielectric layer (120) covers the first dielectric layer (110) and the multiple trenches.

Abstract: A test pattern for testing a trench POLY over-etched step is provided. The test pattern is a trench (14) formed on a substrate (1); the trench (14) comprises a bottom surface and two side surfaces extending from the bottom surface; the trench (14) is formed on the substrate (1) with a preset angle of non-90° formed between the longitudinal direction (L) thereof and the longitudinal direction (X) of a wafer scribing trench. The test pattern can extend the scanning length of a step scanning equipment without changing the width of the trench.

Abstract: The present invention belongs to a bonding technical field of biochips or micromechanical electrical devices, more specifically, to a novel method for bonding two solid planes containing silicon, oxygen, metal or other elements at a moderate temperature via surface assembling of active functional groups. The method includes the steps of: (1) cleaning and hydroxylating solid planes of silicon plate, quartz or glass; (2) aminating a hydroxylated surfaces of the substrate; (3) forming a mono-layer or multi-layer assembled film with compound monomers having an active bi-functional or multi-functional group on an aminated substrate surface; and (4) contacting two solid planes with a assembled film having the same or different active functional groups on its surface tightly, and forming covalent bonds at an appropriate temperature, pressure and a vacuum degree.