Patents by Inventor Zheng Luo

Zheng Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6145007
    Abstract: A method of exchanging messages between first and second processors. A pending flag in a first register is polled by the first processor and if the flag is in a first selected logic state, a message is written into a second register with the first processor. The pending flag is set to a second selected logic state with the first processor and an interrupt to the second processor is generated. The message is read from the second register with the second processor when the pending flag is in the second logic state. The pending flag set to the first logic state with the second processor.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: November 7, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Miroslav Dokic, Raghunath Rao, Jeffrey Niehaus, Zheng Luo, James Divine
  • Patent number: 6101598
    Abstract: A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is interrupted. An input ready bit is set and first word from in the register is read with the target processor. A number of words in the sequence to follow the first word determined from the first word. A word counter is set and the input ready bit is cleared with the target processor. The target processor is returned to main code execution.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: August 8, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Miroslav Dokic, Raghunath Rao, Zheng Luo, Jeffrey Niehaus, James Divine
  • Patent number: 6081783
    Abstract: An audio decoder 100 for operating on a received compressed audio data stream compressed using an algorithm employing transform encoding and a bit allocation routine. A first processor 200 performs a first set of operations on the received compressed audio data stream including parsing the compressed audio data stream, recovering data fields within the compressed audio data stream, calculating a bit allocation, and passing frequency domain coefficients to shared memory. A second digital signal processor 100b performs a second set of operations on data passed from the first digital signal processor to shared memory including performing inverse transform operations on the data passed from the first digital signal processor.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: June 27, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: James Divine, Jeffrey Niehaus, Miroslav Dokic, Raghunath Rao, Terry Ritchie, Baker Scott, III, John Pacourek, Zheng Luo
  • Patent number: 6012142
    Abstract: A message is transferred from external device through a first processor and from the first processor to a second processor. A check is made that the message passed to the second processor without error. The message is interpreted by a selected one of the first and second processors. Boot operations are performed by the selected processor in response to the interpretation of the message.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: January 4, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Miroslav Dokic, Raghunath Rao, Terry Ritchie, James Divine, Jeffrey Niehaus, Zheng Luo