Abstract: The present disclosure discloses a resistive sub-module hybrid MMC and a direct current fault processing strategy thereof. The hybrid MMC prevents fault current from entering a direct current system from the alternating current side by artificially creating three-phase earthing short circuit on the alternating current side of a converter during the direct current fault processing process, and can reduce the number of required power electronic devices compared with the module hybrid MMC. At the same time, the direct current fault processing speed of the hybrid MMC is fast, and the duration of the artificially creating three-phase short circuit fault in the fault processing process is less than 60 ms, which will not have a great impact on the alternating current system. The present disclosure greatly reduces the cost of building an overhead line high-voltage flexible direct current transmission system, and has very strong reference significance and use value in engineering.

Abstract: Innovations in unified intra block copy (“BC”) and inter prediction modes are presented. In some example implementations, bitstream syntax, semantics of syntax elements and many coding/decoding processes for inter prediction mode are reused or slightly modified to enable intra BC prediction for blocks of a frame. For example, to provide intra BC prediction for a current block of a current picture, a motion compensation process applies a motion vector that indicates a displacement within the current picture, with the current picture being used as a reference picture for the motion compensation process. With this unification of syntax, semantics and coding/decoding processes, various coding/decoding tools designed for inter prediction mode, such as advanced motion vector prediction, merge mode and skip mode, can also be applied when intra BC prediction is used, which simplifies implementation of intra BC prediction.

Abstract: A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.

Abstract: A method forms an air gap metal tip structure for (ESD) protection. The method forms an air chamber, from an upper substrate and a lower substate disposed below the upper substrate, within which a first metal tip and a second metal tip are disposed. The first and second metal tips are disposed along at least one horizontal axis parallel to the upper and lower substrates. The chamber includes a portion between points of the metal tips, such that oxygen trapped in the chamber is converted into ozone responsive to an arc between the metal tips to dissipate the arc, and the ozone is decomposed back into the oxygen responsive to an arc absence between the metal tips to maintain the ESD protection for subsequent arcs. An under fill level is disposed between the lower and upper substrates, and above one or more layers having the first and second metal tips.

Abstract: An air gap metal tip structure is provided for (ESD) protection. The structure includes first and second metal tips disposed along at least one horizontal axis that is parallel to a upper substrate and a lower substrate. The structure includes an air chamber formed between the upper and lower substrate within which the first metal tip and the second metal tip are disposed. The air chamber includes a portion between points of the metal tips. The structure includes an under fill level disposed between the lower and upper substrates, and above one or more layers having the metal tips. Oxygen trapped in the air chamber is converted into ozone responsive to an arc between the metal tips to dissipate the arc, and the ozone is decomposed back into the oxygen responsive to an absence of the arc between the metal tips to maintain the ESD protection for subsequent arcs.

Abstract: RRAM devices with tunable forming voltage are provided herein. A method of forming an RRAM device includes: depositing a first dielectric layer on a substrate; forming metal pads in the first dielectric layer; depositing a capping layer onto the first dielectric layer; forming heating elements in the capping layer in contact with the metal pads; forming an RRAM stack on the capping layer; patterning the RRAM stack into an RRAM cell(s) including a bottom electrode, a high-? switching layer disposed on the bottom electrode, and a top electrode disposed on the high-? switching layer; depositing a second dielectric layer over the RRAM cell(s); and forming a contact to the top electrode in the second dielectric layer. An RRAM device and a method of operating an RRAM device are also provided.

Abstract: One embodiment can provide an intelligent robotic system. The intelligent robotic system can include at least one multi-axis robotic arm, at least one gripper attached to the multi-axis robotic arm for picking up a component, a machine vision system comprising at least a three-dimensional (3D) surfacing-imaging module for detecting 3D pose information associated with the component, and a control module configured to control movements of the multi-axis robotic arm and the gripper based on the detected 3D pose of the component.

Abstract: A semiconductor structure is provided. The structure includes a RRAM cell having a first end and a second end. The second end is connected to a first potential. The structure includes a decoupling capacitor having a first end connected in series with the first end of the RRAM cell and a second end connected to a second potential. The structure includes a FET arranged across the capacitor to form a bridged capacitor by having a FET source connected to the first end of the capacitor and a FET drain connected to the second end of the capacitor. A paired activation and subsequent deactivation of the FET enables a short protection mode of the capacitor that provides a series resistance above a threshold amount, between the second potential and the first end of the RRAM cell, responsive to a detected short of the capacitor from the supply to the first potential.

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.

Abstract: One embodiment can provide a machine-vision system. The machine-vision system can include a structured-light projector, a first camera positioned on a first side of the structured-light projector, and a second camera positioned on a second side of the structured-light projector. The first and second cameras are configured to capture images under illumination of the structured-light projector. The structured-light projector can include a laser-based light source.

Abstract: The present invention provides RRAM devices with tunable forming voltage. In one aspect, a method of forming an RRAM device includes: depositing a first dielectric layer on a substrate; forming metal pads in the first dielectric layer; depositing a capping layer onto the first dielectric layer; forming heating elements in the capping layer in contact with the metal pads; forming an RRAM stack on the capping layer; patterning the RRAM stack into an RRAM cell(s) including a bottom electrode, a high-? switching layer disposed on the bottom electrode, and a top electrode disposed on the high-? switching layer; depositing a second dielectric layer over the RRAM cell(s); and forming a contact to the top electrode in the second dielectric layer. An RRAM device and a method of operating an RRAM device are also provided.

Abstract: An integrated semiconductor device includes a substrate, a first vertical transistor, and a second vertical transistor. The substrate has a first substrate region and a second substrate region. The first vertical transistor is disposed on the substrate in the first substrate region. The first vertical transistor is n-type field-effect vertical transistor (n-VFET) with a first channel crystalline orientation. The second vertical transistor is disposed on the substrate in the second substrate region. The second vertical transistor is p-type field-effect vertical transistor (p-VFET) with a second channel crystalline orientation. The first channel crystalline orientation is different from the second channel orientation. A common bottom source and drain region as well as common bottom and top spacers regions are provided for the first vertical transistor and the second vertical transistor.

Abstract: Innovations in encoder-side decisions that use the results of hash-based block matching are presented. For example, some of the innovations relate to ways of building hash tables that include some (but not all) uniform blocks. Other innovations relate to ways of determining motion vector resolution based on results of hash-based block matching. Still other innovations relate to scene change detection, including long-term reference picture selection and picture quality determination during encoding.

Abstract: A method is presented for forming a nanowire electrode. The method includes forming a plurality of nanowires over a first substrate, depositing a conducting layer over the plurality of nanowires, forming solder bumps and electrical interconnections over a second flexible substrate, and integrating nanowire electrode arrays to the second flexible substrate. The plurality of nanowires are silicon (Si) nanowires, the Si nanowires used as probes to penetrate skin of a subject to achieve electrical biopotential signals. The plurality of nanowires are formed over the first substrate by metal-assisted chemical etching.

Abstract: A method for downloading an application includes, after learning that an application is downloaded by a second user equipment, sending, by a first user equipment that has an association relationship with the second user equipment, a downloading request for the application downloaded by the second user equipment to an application server, where the downloading request carries capability information of the first user equipment, and receiving, by the first user equipment, an application to be downloaded, where the application matches the capability information of the first user equipment and is sent by the application server.

Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.

Abstract: A technique relates to a semiconductor device. A rare earth material is formed on a substrate. An isolation layer is formed at an interface of the rare earth material and the substrate. Channel layers are formed over the isolation layer. Source or drain (S/D) regions are formed on the isolation layer.

Abstract: Innovations in encoder-side decisions that use the results of hash-based block matching are presented. For example, some of the innovations relate to ways of building hash tables that include some (but not all) uniform blocks. Other innovations relate to ways of determining motion vector resolution based on results of hash-based block matching. Still other innovations relate to scene change detection, including long-term reference picture selection and picture quality determination during encoding.

Abstract: An apparatus and method of operating the apparatus are disclosed, where the apparatus has translation circuitry to perform translations of input data to generate a translation response comprising translated data. The translation is performed in dependence on translation configuration data stored in data storage. A processing element determines an associated error detection code in dependence on the input data and on the translated data, and causes the translation configuration data and the associated error detection code to be stored in the data storage. When translation of the input data is performed by the translation circuitry the translation configuration data and its associated error detection code are retrieved from the data storage and the input data is translated into the translated data in dependence on the translation configuration data. A verification error detection code is calculated in dependence on the input data and on the translated data.

Abstract: Provided is a control method for a parallel MMC unit of a LCC-MMC hybrid cascade converter station. The control strategy includes: 1) numbering all MMC units connected in parallel in a MMC valve manifold; (2) for a MMC unit using a constant direct-current voltage control manner, calculating a direct-current instruction value of the MMC unit according to a direct-current measurement value; (3) for a MMC unit using a constant active power control manner, calculating an active power instruction value of the MMC unit according to the rated capacity of the MMC unit and a direct-current instruction value of a system rectifier station; (4) for the MMC unit using the constant direct-current voltage control manner, correcting a direct-current voltage instruction value of the MMC unit by using the direct-current instruction value and the direct-current measurement value, and controlling the MMC unit according to the corrected direct-current voltage instruction value.