Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate statistics of a region of a memory circuit as part of a read scrub of the region. The region may have multiple units of data. The memory circuit may be configured to store the data in a nonvolatile condition. The second circuit is generally configured to (i) track one or more parameters of the region based on the statistics, (ii) determine when one or more of the statistics of one or more outliers of the units in the region exceeds a corresponding threshold and (iii) track the parameters of the outlier units separately from the parameters of the region in response to exceeding the corresponding threshold. The parameters generally control one or more reference voltages used to read the data from the region.

Abstract: A read threshold voltage for a memory is adjusted based on a bit error rate based on decoded data for a plurality of read threshold voltages. The read threshold voltage can be adjusted by reading the memory at a current read threshold voltage to obtain a read value; applying a hard decision decoder to the read value; determining if the hard decision decoder converges for the read value to a converged word; storing bits corresponding to the converged word as reference bits and, if the hard decision decoder converges, (i) computing a bit error rate for the current read threshold voltage based on the reference bits; (ii) adjusting the current read reference voltage to a new read threshold voltage; and (iii) reading the memory at the new read threshold voltage to obtain a new read value, until a threshold is satisfied; and once the threshold is satisfied, selecting the read threshold voltage based on the bit error rates.

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

Abstract: Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.

Abstract: Channel information and channel conditions determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is so adjusted. This latter approach is advantageous in that relatively fewer adjustments will be made during normal read operations.

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.

Abstract: A read threshold voltage for a memory is adjusted based on a bit error rate based on decoded data for a plurality of read threshold voltages. The read threshold voltage can be adjusted by reading the memory at a current read threshold voltage to obtain a read value; applying a hard decision decoder to the read value; determining if the hard decision decoder converges for the read value to a converged word; storing bits corresponding to the converged word as reference bits and, if the hard decision decoder converges, (i) computing a bit error rate for the current read threshold voltage based on the reference bits; (ii) adjusting the current read reference voltage to a new read threshold voltage; and (iii) reading the memory at the new read threshold voltage to obtain a new read value, until a threshold is satisfied; and once the threshold is satisfied, selecting the read threshold voltage based on the bit error rates.

Abstract: Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.

Abstract: Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.

Abstract: Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is adjusted with that precision.

Abstract: A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping.

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to blocks of the memory that are not marked as bad on a block list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to perform a plurality of scans on the memory. The scans are configured to (a) identify the bad blocks, and (b) mark the bad blocks as bad on the block list.

Abstract: A method for recovery after a power failure. The method generally includes a step of searching at least some of a plurality of pages of a memory to find a first erased page in response to an unsafe power down. A step may move stored data located between a particular word line in the memory that contains the first erased page and a previous word line that is at least two word lines before the particular word line. Another step may write new data starting in a subsequent word line that is the at least two word lines after the particular word line that contains the first erased page.

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. In one embodiment, the systems and methods include providing a flash memory circuit including a superset of memory cells, accessing a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells, and based at least in part on determining that the group of memory cells was a last written group of memory cells, re-accessing a data set from the group of memory cells using a last written reference value to distinguish bit values in the group of memory cells.

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

Abstract: A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping.

Abstract: Methods and apparatus are provided for collecting cell-level statistics for detection and decoding in flash memories. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in a page of the flash memory device; and generating cell-level statistics for the flash memory device based on a probability that a data pattern was read from the plurality of bits given that a particular pattern was written to the plurality of bits. The cell-level statistics are optionally generated substantially simultaneously with a reading of the read values, for example, as part of a read scrub process. The cell-level statistics can be used to convert the read values for the plurality of bits to a reliability value for a bit among the plurality of bits.

Abstract: A method for data recovery after a power failure is disclosed. The method may include steps (A) to (D). Step (A) may determine that a last power-down of a solid-state drive was an unsafe power-down. Step (B) may search at least some of a plurality of pages of a nonvolatile memory of the solid-state drive to define an unsafe zone in response to the determining that the last power-down of the solid-state drive was the unsafe power-down. Step (C) may define a pad zone comprising one or more of the pages subsequent to the unsafe zone. Step (D) may resume operation of the solid-state drive by writing new data subsequent to the pad zone.

Abstract: Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the flash cells ensures that mis-programming of the reference voltage ranges will not occur.