Patents by Inventor Zhengang Chen

Zhengang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • REDUCTION OR ELIMINATION OF A LATENCY PENALTY ASSOCIATED WITH ADJUSTING READ THRESHOLDS FOR NON-VOLATILE MEMORY
    Publication number: 20190348133
    Abstract: Channel information and channel conditions determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is so adjusted. This latter approach is advantageous in that relatively fewer adjustments will be made during normal read operations.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 14, 2019
    Inventors: Zhengang Chen, Erich F. Haratsch, Sundararajan Sankaranarayanan
  • Accelerated soft read for multi-level cell nonvolatile memories
    Patent number: 10468096
    Abstract: A memory device includes a memory array comprising multi-level memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array. A given one of the accelerated soft read operations directed to a non-upper page of the memory array comprises at least one hard read operation directed to a corresponding upper page of the memory array. The given accelerated soft read operation may comprise a sequence of multiple hard read operations including a hard read operation directed to the non-upper page and one or more hard read operations directed to the corresponding upper page.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: November 5, 2019
    Assignee: Seagate Technology LLC
    Inventors: Zhengang Chen, Hao Zhong
  • Systems and methods for latency based data recycling in a solid state memory system
    Patent number: 10437513
    Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 8, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Yu Cai, Yunxiang Wu, Ning Chen, Erich F. Haratsch, Zhengang Chen
  • Manufacturer self-test for solid-state drives
    Patent number: 10410736
    Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: September 10, 2019
    Assignee: Seagate Technology LLC
    Inventors: Zhengang Chen, David Patmore, Yingji Ju, Erich F. Haratsch
  • Priori information based post-processing in low-density parity-check code decoders
    Patent number: 10396817
    Abstract: A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: August 27, 2019
    Assignee: Seagate Technology LLC
    Inventors: Zhengang Chen, Abdelhakim S. Alhussein, Erich F. Haratsch
  • Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory
    Patent number: 10388385
    Abstract: Channel information and channel conditions determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is so adjusted. This latter approach is advantageous in that relatively fewer adjustments will be made during normal read operations.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 20, 2019
    Assignee: Seagate Technology LLC
    Inventors: Zhengang Chen, Erich F. Haratsch, Sundararajan Sankaranarayanan
  • Internal copy-back with read-verify
    Patent number: 10353622
    Abstract: Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: July 16, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Erich F. Haratsch, Zhengang Chen, Stephen Hanna, Abdelhakim Alhussien
  • Data compression using partial statistics
    Patent number: 10303402
    Abstract: A data storage device includes at least one data storage medium and a controller that is operably coupled to the at least one data storage medium. The controller receives the bit stream in a data storage device and performs a first level of compression on the received bit stream to obtain a symbol frame including a plurality of symbols. The controller encodes an initial portion of the plurality of symbols contained in the symbol frame by a fixed encoding scheme. The controller also collects statistics for the initial portion of the symbol frame. The controller then selects at least one data compression algorithm based on the collected statistics. The controller then performs compression encoding on a remaining portion of the symbol frame with the selected at least one data compression algorithm.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: May 28, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Hongmei Xie, Zhengang Chen, Bijan Eskandari-Gharnin, Erich F. Haratsch
  • Systems and methods for soft decision generation in a solid state memory system
    Patent number: 10298264
    Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data processing system includes a solid state memory device, a soft data generation circuit operable to receive multiple instances of an element of a read data set accessed from the solid state memory device, and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, and a data decoder circuit operable to yield a decoded output from the soft data.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: May 21, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Zhengang Chen, Yunxiang Wu, Erich F. Haratsch
  • Flash memory read error recovery with soft-decision decode
    Patent number: 10073734
    Abstract: An apparatus comprising a memory and a controller. The memory may be configured to store data. The controller may process a plurality of input/output requests to read/write to/from the memory. The controller may generate read data by performing a hard-decision decode on a codeword received from the memory. If the hard-decision decode fails, the controller may enter an error-recovery process comprising a plurality of recovery procedures. At least one of the recovery procedures may apply an inter-cell interference cancellation technique. The error-recovery process may (a) determine parameters for a soft-decision decode by performing one of the recovery procedures on the codeword, (b) execute the soft-decision decode using the parameters from the recovery procedure performed to generate the read data and (c) if the soft-decision decode fails, repeat (a) and (b) using a next one of the recovery procedures.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: September 11, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Erich F. Haratsch, Jeremy Werner, Zhengang Chen, Earl T. Cohen, Yunxiang Wu, Ning Chen
  • Nonvolatile memory recovery after power failure during write operations or erase operations
    Patent number: 10048879
    Abstract: A method for recovery after a power failure. The method generally includes a step of searching at least some of a plurality of pages of a memory to find a first erased page in response to an unsafe power down. A step may move stored data located between a particular word line in the memory that contains the first erased page and a previous word line that is at least two word lines before the particular word line. Another step may write new data starting in a subsequent word line that is the at least two word lines after the particular word line that contains the first erased page.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: August 14, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Zhengang Chen, Earl T. Cohen, Alex G. Tang
  • SYSTEMS AND METHODS FOR SOFT DECISION GENERATION IN A SOLID STATE MEMORY SYSTEM
    Publication number: 20180226991
    Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data processing system includes a solid state memory device, a soft data generation circuit operable to receive multiple instances of an element of a read data set accessed from the solid state memory device, and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, and a data decoder circuit operable to yield a decoded output from the soft data.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 9, 2018
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Zhengang Chen, Yunxiang Wu, Erich F. Haratsch
  • Flash channel with selective decoder likelihood dampening
    Patent number: 10019313
    Abstract: An apparatus for reading a flash memory includes a read controller operable to read the flash memory to yield read patterns, a likelihood generator operable to map the read patterns to likelihood values, a decoder operable to decode the likelihood values, a data state storage operable to retrieve the likelihood values for which decoding failed, and a selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 10, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Zhengang Chen, Yunxiang Wu, AbdelHakim S Alhussien, Erich F Haratsch
  • CAPACITANCE COUPLING PARAMETER ESTIMATION IN FLASH MEMORIES
    Publication number: 20180180654
    Abstract: A method for capacitance coupling parameter estimation includes determining a plurality of mean voltages among a plurality of memory cells of the memory in each of a plurality of cases related to inter-cell interference, generating a plurality of middle state mean voltages in response to the mean voltages, and adjusting one or more threshold voltages used to read from the memory based on the middle state mean voltages to operate independently of knowledge of middle state distributions in the memory cells.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Inventors: Meysam Asadi, Zhengang Chen, Erich F. Haratsch
  • Periodically Updating a Log Likelihood Ratio (LLR) Table in a Flash Memory Controller
    Publication number: 20180158536
    Abstract: Log likelihood ratio (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.
    Type: Application
    Filed: January 30, 2018
    Publication date: June 7, 2018
    Inventors: Yunxiang Wu, Yu Cai, Zhengang Chen, Erich Haratsch
  • Systems and methods for soft decision generation in a solid state memory system
    Patent number: 9941901
    Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data processing system includes a solid state memory device, a soft data generation circuit operable to receive multiple instances of an element of a read data set accessed from the solid state memory device, and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, and a data decoder circuit operable to yield a decoded output from the soft data.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: April 10, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Zhengang Chen, Yunxiang Wu, Erich F. Haratsch
  • Capacitance coupling parameter estimation in flash memories
    Patent number: 9934867
    Abstract: A method for capacitance coupling parameter estimation is disclosed. Step (A) of the method determines a plurality of voltages in a plurality of memory cells of a nonvolatile memory in response to a plurality of writes to the memory cells. The voltages are determined in each of a plurality of cases related to inter-cell interference. Step (B) generates a system of equations of a capacitance coupling model in response to the voltages from all of the cases. Step (C) generates one or more parameters in response to the system of equations. The parameters include one or more couplings between a perturbed memory cell and a plurality of neighboring memory cells adjacent to the perturbed memory cell.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: April 3, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Meysam Asadi, Zhengang Chen, Erich F. Haratsch
  • Systems and methods for last written page handling in a memory device
    Patent number: 9928139
    Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. In one embodiment, the systems and methods include providing a flash memory circuit including a superset of memory cells, accessing a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells, and based at least in part on determining that the group of memory cells was a last written group of memory cells, re-accessing a data set from the group of memory cells using a last written reference value to distinguish bit values in the group of memory cells.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: March 27, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Zhengang Chen, Yu Cai, Erich F. Haratsch, Zhimin Dong
  • Periodically updating a log likelihood ratio (LLR) table in a flash memory controller
    Patent number: 9916906
    Abstract: Log likelihood ration (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 13, 2018
    Assignee: Seagate Technology LLC
    Inventors: Yunxiang Wu, Yu Cai, Zhengang Chen, Erich Haratsch
  • DATA COMPRESSION USING PARTIAL STATISTICS
    Publication number: 20180039426
    Abstract: A data storage device includes at least one data storage medium and a controller that is operably coupled to the at least one data storage medium. The controller receives the bit stream in a data storage device and performs a first level of compression on the received bit stream to obtain a symbol frame including a plurality of symbols. The controller encodes an initial portion of the plurality of symbols contained in the symbol frame by a fixed encoding scheme. The controller also collects statistics for the initial portion of the symbol frame. The controller then selects at least one data compression algorithm based on the collected statistics. The controller then performs compression encoding on a remaining portion of the symbol frame with the selected at least one data compression algorithm.
    Type: Application
    Filed: August 2, 2016
    Publication date: February 8, 2018
    Inventors: Hongmei Xie, Zhengang Chen, Bijan Eskandari-Gharnin, Erich F. Haratsch