Abstract: A vacuum transistor includes a substrate and a first terminal formed on the substrate. A piezoelectric element has a second terminal formed on the piezoelectric element, wherein the piezoelectric element is provided over the first terminal to provide a gap between the first terminal and the second terminal. The gap is adjusted in accordance with an electrical field on the piezoelectric element.

Abstract: A bamboo tableware processing method, comprising the following steps: S1, using a clamping member (4) to clamp a plurality of bamboo chips; S2, controlling a milling cutter (2) to rotate; and S3, moving the clamping member and/or the milling cutter to cut the plurality of bamboo chips by means of the milling cutter. Also provided is a bamboo tableware processing apparatus. According to the processing method, a plurality of bamboo chips are processed simultaneously, the processing efficiency is improved, and the quality of the product is improved. Moreover, a plurality of bamboo chips are subjected to high-speed milling and cutting at one time, burrs may not be generated at edges of the bamboo chips, and the step of polishing for burr removing is omitted.

Abstract: A field effect transistor includes an exposed channel region disposed between a source region and a drain region. A gate electrode is disposed over the exposed channel region. An electrolyte gel is disposed between the gate electrode and the exposed channel region, wherein ions are immobilized in the electrolyte gel below a transition temperature and mobilized above the transition temperature to increase device resistance.

Abstract: An integrated circuit includes an array of devices with a logic pattern to implement a physically unclonable function (PUF) for chip authentication. The logic pattern is determined in accordance with processing variations during the manufacturing. The array of devices includes one or more components having a first state and one or more components having a second state. A combination of the first and second states provides the logic pattern.

Abstract: A three-dimensional integration of synapse circuitry is formed. One or more neuron layers each comprises a plurality of computing elements, and one or more synapse layers each comprising an array of memory elements are formed on top of the one or more neuron layers. A plurality of staggered through-silicon vias (TSVs) connect the one or more neuron layers to the one or more synapse layers and operate as communication links between one or more computing elements in the one or more neuron layers and one or more memory elements in the one or more synapse layers.

Abstract: A vacuum transistor includes a substrate and a first terminal formed on the substrate. A piezoelectric element has a second terminal formed on the piezoelectric element, wherein the piezoelectric element is provided over the first terminal to provide a gap between the first terminal and the second terminal. The gap is adjusted in accordance with an electrical field on the piezoelectric element.

Abstract: A nanoparticle includes a cuboid base including a semiconductor material, and a plurality of surfaces formed on the base and including a plurality of functionalities, respectively.

Abstract: The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.

Abstract: A sensor includes a semiconductor substrate having first pointed nodes extending into a channel from a first side of the channel. Second pointed nodes extend into the channel from a second side of the channel, which is opposite the first side. The second pointed nodes being self-aligned to the first pointed nodes on the opposite side of the channel. The first pointed nodes and the second pointed nodes are connected to a circuit to detect particles in the channel.

Abstract: A vacuum transistor includes a substrate and a first terminal formed on the substrate. A piezoelectric element has a second terminal formed on the piezoelectric element, wherein the piezoelectric element is provided over the first terminal to provide a gap between the first terminal and the second terminal. The gap is adjusted in accordance with an electrical field on the piezoelectric element.

Abstract: A semiconductor chip includes a chip substrate; a self-destructive layer arranged on the chip substrate, the self-destructive layer including a pyrophoric reactant; and a sealant layer arranged on a surface of the self-destructive layer, on sidewalls of the self-destructive layer, and on the chip substrate such that the sealant layer forms a package seal on the semiconductor chip; wherein the pyrophoric reactant ignites spontaneously upon exposure to air.

Abstract: A field effect transistor includes an exposed channel region disposed between a source region and a drain region. A gate electrode is disposed over the exposed channel region. An electrolyte gel is disposed between the gate electrode and the exposed channel region, wherein ions are immobilized in the electrolyte gel below a transition temperature and mobilized above the transition temperature to increase device resistance.

Abstract: A vacuum transistor includes a substrate and a first terminal formed on the substrate. A piezoelectric element has a second terminal formed on the piezoelectric element, wherein the piezoelectric element is provided over the first terminal to provide a gap between the first terminal and the second terminal. The gap is adjusted in accordance with an electrical field on the piezoelectric element.

Abstract: A field effect transistor includes an exposed channel region disposed between a source region and a drain region. A gate electrode is disposed over the exposed channel region. An electrolyte gel is disposed between the gate electrode and the exposed channel region, wherein ions are immobilized in the electrolyte gel below a transition temperature and mobilized above the transition temperature to increase device resistance.

Abstract: The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.

Abstract: A nanoparticle includes a cuboid base including a semiconductor material, and a plurality of surfaces formed on the base and including a plurality of functionalities, respectively.

Abstract: A method of forming a nanoparticle includes forming a layer of semiconductor material on a substrate, forming a first layer on the semiconductor material, and etching the semiconductor layer to form the nanoparticle including the first layer on a first side of the nanoparticle and the semiconductor material on a second side of the nanoparticle.