Abstract: The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.

Abstract: The subject disclosure relates to techniques for providing semiconductor chip security using piezoelectricity. According to an embodiment, an apparatus is provided that comprises an integrated circuit chip comprising a pass transistor that electrically connects two or more electrical components of the integrated circuit chip. The apparatus further comprises a piezoelectric element electrically connected to a gate electrode of the pass transistor; and a packaging component that is physically connected to the piezoelectric element and applies a mechanical force to the piezoelectric element, wherein the piezoelectric element generates and provides a voltage to the gate electrode as a result of the mechanical force, thereby causing the pass transistor to be in an on-state. In one implementation, the two or more electrical components comprise a circuit and a power source. In another implementation, the two or more electrical components comprise two circuits.

Abstract: A semiconductor device includes a first dielectric layer formed on a second dielectric layer and planar contacts formed in the second dielectric layer. The planar contacts are spaced apart to form a gap therebetween. The first dielectric layer includes a thermally conductive dielectric layer and is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed between the planar contacts over the gap and in contact with at least the thermally conductive dielectric layer in the gap.

Abstract: A dosimetry device includes a first chamber formed on a substrate with a first decomposable barrier sensitive to radiation and a first chemical component. A second chamber is formed on the substrate in proximity of the first chamber and includes a second decomposable barrier sensitive to radiation and a second chemical component. Upon a radiation event, decomposition of the first and second barriers of the first and second chambers permits a mixing of the first and second chemical components to cause a visible change of the dosimetry device.

Abstract: Semiconductor devices include a thin channel region formed on a buried insulator. A source and drain region is formed on the buried insulator, separated from the channel region by notches. A gate structure is formed on the thin channel region.

Abstract: A semiconductor device includes a first dielectric layer formed from a thermally conductive dielectric material. Contacts are formed in the first dielectric layer, the planar contacts being spaced apart to form a gap therebetween. The thermally conductive dielectric material of the first dielectric layer is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed laterally across the gap between the planar contacts and in direct contact with at least the thermally conductive dielectric material in the gap.

Abstract: A dosimetry device includes a first chamber formed on a substrate with a first decomposable barrier sensitive to radiation and a first chemical component. A second chamber is formed on the substrate in proximity of the first chamber and includes a second decomposable barrier sensitive to radiation and a second chemical component. Upon a radiation event, decomposition of the first and second barriers of the first and second chambers permits a mixing of the first and second chemical components to cause a visible change of the dosimetry device.

Abstract: A dosimetry device includes a first chamber formed on a substrate with a first decomposable barrier sensitive to radiation and a first chemical component. A second chamber is formed on the substrate in proximity of the first chamber and includes a second decomposable barrier sensitive to radiation and a second chemical component. Upon a radiation event, decomposition of the first and second barriers of the first and second chambers permits a mixing of the first and second chemical components to cause a visible change of the dosimetry device.

Abstract: A method of arranging at least one carbon nanotube on a semiconductor substrate includes depositing the at least one carbon nanotube on a dielectric layer of the semiconductor device. The method further includes arranging the at least one carbon nanotube on the dielectric layer in response to applying a voltage potential to an electrically conductive electrode of the semiconductor device, and applying a ground potential to an electrically conductive semiconductor layer of the semiconductor device.

Abstract: Semiconductor devices include a thin channel region formed on a buried insulator. A source and drain region is formed on the buried insulator, separated from the channel region by notches. A gate structure is formed on the thin channel region.

Abstract: A transistor device includes an array of fin structures arranged on a substrate, each of the fin structures being vertically alternating stacks of a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point; one or more carbon nanotubes (CNTs) suspended between the fin structures and contacting a side surface of the second isoelectric point material in the fin structures; a gate wrapped around the array of CNTs; and source and drain contacts arranged over the fin structures; wherein each of the fin structures have a trapezoid shape or parallel sides that are oriented about 90° with respect to the substrate.

Abstract: An integrated circuit includes an array of devices with a logic pattern to implement a physically unclonable function (PUF) for chip authentication. The logic pattern is determined in accordance with processing variations during the manufacturing. The array of devices includes one or more components having a first state and one or more components having a second state. A combination of the first and second states provides the logic pattern.

Abstract: Vacuum transistors with carbon nanotube as the collector and/or emitter electrodes are provided. In one aspect, a method for forming a vacuum transistor includes the steps of: covering a substrate with an insulating layer; forming a back gate(s) in the insulating layer; depositing a gate dielectric over the back gate; forming a carbon nanotube layer on the gate dielectric; patterning the carbon nanotube layer to provide first/second portions thereof over first/second sides of the back gate, separated from one another by a gap G, which serve as emitter and collector electrodes; forming a vacuum channel in the gate dielectric; and forming metal contacts to the emitter and collector electrodes. Vacuum transistors are also provided.

Abstract: A vacuum transistor includes a substrate and a first terminal formed on the substrate. A piezoelectric element has a second terminal formed on the piezoelectric element, wherein the piezoelectric element is provided over the first terminal to provide a gap between the first terminal and the second terminal. The gap is adjusted in accordance with an electrical field on the piezoelectric element.

Abstract: A vacuum transistor includes a substrate and a first terminal formed on the substrate. A piezoelectric element has a second terminal formed on the piezoelectric element, wherein the piezoelectric element is provided over the first terminal to provide a gap between the first terminal and the second terminal. The gap is adjusted in accordance with an electrical field on the piezoelectric element.

Abstract: Semiconductor devices and methods of making the same include forming a gate structure on a thin semiconductor layer. Additional semiconductor material is formed on the thin semiconductor layer. The thin semiconductor layer is etched back and the additional semiconductor material to form source and drain regions and a channel region, with notches separating the source and drain region from the channel region.

Abstract: A technique relates to a vertical device. A gate is embedded in a transparent substrate. A gate dielectric material is disposed on the gate. A nanotube film is disposed on the gate dielectric material. A quantum dot light emitting diode is disposed on a portion of the nanotube film.

Abstract: An integrated circuit includes an array of devices including a physically unclonable function (PUF) for chip authentication. A logic pattern is stored in the devices. The logic pattern is determined in accordance with processing variations during manufacture of the array. The logic pattern is represented with a first state for one or more devices with contact shorts and a second state with one or more devices without contact shorts.

Abstract: A technique relates to a vertical device. A gate is embedded in a transparent substrate. A gate dielectric material is disposed on the gate. A nanotube film is disposed on the gate dielectric material. A quantum dot light emitting diode is disposed on a portion of the nanotube film.

Abstract: A method of arranging at least one carbon nanotube on a semiconductor substrate includes depositing the at least one carbon nanotube on a dielectric layer of the semiconductor device. The method further includes arranging the at least one carbon nanotube on the dielectric layer in response to applying a voltage potential to an electrically conductive electrode of the semiconductor device, and applying a ground potential to an electrically conductive semiconductor layer of the semiconductor device.