Abstract: A deep learning-based method for fusing multi-source urban energy data and a storage medium are provided to perform data fusion on multi-source urban energy data found in big data and perform multi-scale and multimodal information fusion by using a cross-modal transformer, thereby implementing cross-modal mutual fusion of multi-source heterogeneous types of data to obtain a fused feature for prediction of a quantity of energy that will be used in the future and a quantity of energy that needs to be produced. The present disclosure proposes a multi-scale cooperative multimodal transformer architecture to enhance an effect of representation learned from an unaligned multimodal sequence. Not only there is a higher degree of correlation in multi-source urban energy data fusion, but also a system becomes more lightweight.

Abstract: According to a transformer-architecture-based method and system for IoT for and smart control of urban integrated energy, urban integrated energy IoT information acquired by a terminal from different areas is output to a server after being standardized into a sequence signal, where energy demand prediction is performed through learning of a deep learning network configured on the server, a smart control network is configured and built by using the deep learning network, real-time prediction processing is performed on the urban integrated energy IoT information acquired in real time, and a result is uploaded to a workstation for reviewing. Based on the transformer architecture, the deep learning network is combined with a fast Fourier transform algorithm and inverse transform on a sequence, and an FFT-Attention mechanism is proposed. Compared with a conventional transformer architecture, frequency domain information of a sequence is given more emphasis.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: A reasonable millisecond time control method for excavation blasting of a tunnel is provided, and includes: acquiring physical mechanical parameters to establish a millisecond blasting model, and designing four dimensions blasting parameters of explosive quantity, hole number, inter-hole millisecond and inter-row millisecond; simulating, based on the millisecond blasting model, a blasting process of an explosive package using blasting parameters to obtain a blasting vibration curve; obtaining single-hole blasting vibration waveforms, solving a vibration synthesis curve through a vibration synthesis theory; comparing the vibration synthesis curve with the blasting vibration curve to obtain a coupling relationship of blasting parameters; determining a target group of explosive quantity and hole numbers, determining a target millisecond through the coupling relationship of blasting parameters, and relating a millisecond blasting control strategy to control, and it is used for tunneling project to reduce cut blas

Abstract: A construction method and system for asset value models in a digital twin engine includes: measuring the level of business importance based on a business model of building energy consumption assets, and constructing a first asset value model according to the business importance; establishing a correlation between the assets and productivity, and constructing a second asset value model according to productivity loss caused by the assets; and calculating the energy use efficiency of a building according to optimal decision variables, predicting the degradation index of the assets through the energy use efficiency, the first asset value model and the second asset value model, and generating a maintenance solution of the assets. The disclosed has ingenious conception and excellent effect, and realizes the accurate evaluation of the asset value by establishing the correlation between the assets and different businesses and different efficiency, generating the optimal and most accurate asset maintenance solution.

Abstract: Embodiments of this application disclose a rule detection method, to increase rule anomaly detection coverage. The method in the embodiments of this application includes: determining, based on an obtained first initial priority corresponding to a first rule, an obtained second current priority corresponding to a second rule, and a determined inclusion relationship between the first rule and the second rule, a first current priority corresponding to the first rule; and then determining, based on a relationship between the first initial priority and the first current priority, whether an anomaly occurs on the first rule.

Abstract: This application provides a traffic classification method and apparatus. The method includes: determining, based on distribution characteristics of concerned bits of a plurality of rules in a first rule set, an effective bit corresponding to the first rule set; determining a hash key value of each rule based on a value of the effective bit of each rule in the first rule set, and storing each rule in the first rule set in at least one of S storage units based on the hash key value, where the first rule set is any one of N rule sets, the N rule sets are stored in the S storage units; and when traffic classification is performed, searching for a corresponding rule in each of the S storage units based on a hash key value of a search key.

Abstract: Embodiments of this application disclose a traffic monitoring method and apparatus, an integrated circuit, and a network device. When the traffic monitoring apparatus receives a packet, after determining that the traffic monitoring apparatus includes an empty first register, the traffic monitoring apparatus updates a value of first information in the first register to a measured value of a target performance indicator of the packet, and increases a value of second information in the first register by 1. The value of the second information in the first register is 0, the first information in the first register indicates a depth of a data bucket that carries a measured value of the target performance indicator of a to-be-monitored packet, and the second information in the first register indicates a quantity of packets that are in received packets and that match the value of the first information in the first register.

Abstract: Embodiments of this application disclose a traffic monitoring method and apparatus, an integrated circuit, and a network device. When the traffic monitoring apparatus receives a packet, after determining that the traffic monitoring apparatus includes an empty first register, the traffic monitoring apparatus updates a value of first information in the first register to a measured value of a target performance indicator of the packet, and increases a value of second information in the first register by 1. The value of the second information in the first register is 0, the first information in the first register indicates a depth of a data bucket that carries a measured value of the target performance indicator of a to-be-monitored packet, and the second information in the first register indicates a quantity of packets that are in received packets and that match the value of the first information in the first register.

Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a selected wordline associated with a set of memory cells to be programmed to a target voltage level representing a programming level. Voltage levels of the selected wordline and one or more unselected wordlines of the memory array are discharged to approximately a ground voltage level and a bitline voltage level is applied to a bitline corresponding to the programming level. The selected wordline and a set of unselected wordlines are charged to approximately a pass voltage level followed by the discharge of the selected wordline to a reverse bias level to establish an erase voltage level on the set of memory cells. The control logic further performs a program verify operation corresponding to the programming level associated with the set of memory cells.

Abstract: Embodiments of this application disclose a traffic monitoring method, an apparatus, an integrated circuit, a network device, and a network system. When receiving a first packet, a traffic collection apparatus determines that a measurement value of a target performance indicator of the first packet matches a value of first information in a first register, updates a value of second information in the first register based on the measurement value of the target performance indicator of the first packet, and increases a value of third information in the first register by 1.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: Apparatus having a string of series-connected memory cells, a plurality of access lines with each access line of the plurality of access lines connected to a control gate of a respective memory cell of the plurality of memory cells, and a controller for access of the string of series-connected memory cells and configured to cause the memory to increase a threshold voltage of a particular memory cell of the string of series-connect memory cells to a voltage level higher than a predetermined pass voltage to be received by a control gate of the particular memory cell during a read operation on the string of series-connected memory cells, and concurrently change a respective data state of each memory cell of a plurality of memory cells of the string of series-connected memory cells.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: Control logic in a memory device causes a first programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a wordline associated with a memory cell to be programmed to a first target voltage level representing a first programming level. The control logic further performs a program verify operation corresponding to the first programming level to determine that a threshold voltage of the memory cell exceeds the first target voltage level. The control logic further causes first data to be stored in a cache, the first data indicating that the threshold voltage of the memory cell exceeds the first target voltage level. The cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the first target voltage level. In view of the second data, a further programming pulse is caused to be applied to the wordline associated with the memory cell at a reduced programming stress level.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: Embodiments of this application disclose a rule detection method, to increase rule anomaly detection coverage. The method in the embodiments of this application includes: determining, based on an obtained first initial priority corresponding to a first rule, an obtained second current priority corresponding to a second rule, and a determined inclusion relationship between the first rule and the second rule, a first current priority corresponding to the first rule; and then determining, based on a relationship between the first initial priority and the first current priority, whether an anomaly occurs on the first rule.

Abstract: This application provides a traffic classification method and apparatus. The method includes: determining, based on distribution characteristics of concerned bits of a plurality of rules in a first rule set, an effective bit corresponding to the first rule set; determining a hash key value of each rule based on a value of the effective bit of each rule in the first rule set, and storing each rule in the first rule set in at least one of S storage units based on the hash key value, where the first rule set is any one of N rule sets, the N rule sets are stored in the S storage units; and when traffic classification is performed, searching for a corresponding rule in each of the S storage units based on a hash key value of a search key.

Abstract: Apparatus having a string of series-connected memory cells, a plurality of access lines with each access line of the plurality of access lines connected to a control gate of a respective memory cell of the plurality of memory cells, and a controller for access of the string of series-connected memory cells and configured to cause the memory to increase a threshold voltage of a particular memory cell of the string of series-connect memory cells to a voltage level higher than a predetermined pass voltage to be received by a control gate of the particular memory cell during a read operation on the string of series-connected memory cells, and concurrently change a respective data state of each memory cell of a plurality of memory cells of the string of series-connected memory cells.

Abstract: Apparatus having a string of series-connected memory cells comprising a plurality of principal memory cells and a plurality of dummy memory cells might have a controller configured to cause the apparatus to apply a first programming pulse to a particular dummy memory cell of the plurality of dummy memory cells sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level sufficient to cause the particular dummy memory cell to remain deactivated during a read operation on the string of series-connected memory cells, and to concurrently apply a second programming pulse to each principal memory cell of the plurality of principal memory cell sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells.