Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. At a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. At a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. In view of the second data, a level shifting operation associated with the memory cell is caused to be executed.

Abstract: The present invention discloses multistage membrane apparatus and a method for separating gases from a crude gas stream a gas to be separated, a main remaining gas and optionally one or more further gas components, wherein in the apparatus comprises a feed stream separation stage, a first permeate separation stage and a second permeate separation stage, each stage being a membrane separation stage with gas separation membranes.

Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. At a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. At a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. In view of the second data, a level shifting operation associated with the memory cell is caused to be executed.

Abstract: Embodiments of this application disclose a traffic monitoring method, an apparatus, an integrated circuit, a network device, and a network system. When receiving a first packet, a traffic collection apparatus determines that a measurement value of a target performance indicator of the first packet matches a value of first information in a first register, updates a value of second information in the first register based on the measurement value of the target performance indicator of the first packet, and increases a value of third information in the first register by 1.

Abstract: Control logic in a memory device causes a first programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a wordline associated with a memory cell to be programmed to a first target voltage level representing a first programming level. The control logic further performs a program verify operation corresponding to the first programming level to determine that a threshold voltage of the memory cell exceeds the first target voltage level. The control logic further causes first data to be stored in a cache, the first data indicating that the threshold voltage of the memory cell exceeds the first target voltage level. The cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the first target voltage level. In view of the second data, a further programming pulse is caused to be applied to the wordline associated with the memory cell at a reduced programming stress level.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: Embodiments of this application disclose a rule detection method, to increase rule anomaly detection coverage. The method in the embodiments of this application includes: determining, based on an obtained first initial priority corresponding to a first rule, an obtained second current priority corresponding to a second rule, and a determined inclusion relationship between the first rule and the second rule, a first current priority corresponding to the first rule; and then determining, based on a relationship between the first initial priority and the first current priority, whether an anomaly occurs on the first rule.

Abstract: This application provides a traffic classification method and apparatus. The method includes: determining, based on distribution characteristics of concerned bits of a plurality of rules in a first rule set, an effective bit corresponding to the first rule set; determining a hash key value of each rule based on a value of the effective bit of each rule in the first rule set, and storing each rule in the first rule set in at least one of S storage units based on the hash key value, where the first rule set is any one of N rule sets, the N rule sets are stored in the S storage units; and when traffic classification is performed, searching for a corresponding rule in each of the S storage units based on a hash key value of a search key.

Abstract: Embodiments of this application disclose a traffic monitoring method and apparatus, an integrated circuit, and a network device. When the traffic monitoring apparatus receives a packet, after determining that the traffic monitoring apparatus includes an empty first register, the traffic monitoring apparatus updates a value of first information in the first register to a measured value of a target performance indicator of the packet, and increases a value of second information in the first register by 1. The value of the second information in the first register is 0, the first information in the first register indicates a depth of a data bucket that carries a measured value of the target performance indicator of a to-be-monitored packet, and the second information in the first register indicates a quantity of packets that are in received packets and that match the value of the first information in the first register.

Abstract: Embodiments of this application disclose a traffic monitoring method and apparatus, an integrated circuit, and a network device. When the traffic monitoring apparatus receives a packet, after determining that the traffic monitoring apparatus includes an empty first register, the traffic monitoring apparatus updates a value of first information in the first register to a measured value of a target performance indicator of the packet, and increases a value of second information in the first register by 1. The value of the second information in the first register is 0, the first information in the first register indicates a depth of a data bucket that carries a measured value of the target performance indicator of a to-be-monitored packet, and the second information in the first register indicates a quantity of packets that are in received packets and that match the value of the first information in the first register.

Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a selected wordline associated with a set of memory cells to be programmed to a target voltage level representing a programming level. Voltage levels of the selected wordline and one or more unselected wordlines of the memory array are discharged to approximately a ground voltage level and a bitline voltage level is applied to a bitline corresponding to the programming level. The selected wordline and a set of unselected wordlines are charged to approximately a pass voltage level followed by the discharge of the selected wordline to a reverse bias level to establish an erase voltage level on the set of memory cells. The control logic further performs a program verify operation corresponding to the programming level associated with the set of memory cells.

Abstract: Embodiments of this application disclose a traffic monitoring method, an apparatus, an integrated circuit, a network device, and a network system. When receiving a first packet, a traffic collection apparatus determines that a measurement value of a target performance indicator of the first packet matches a value of first information in a first register, updates a value of second information in the first register based on the measurement value of the target performance indicator of the first packet, and increases a value of third information in the first register by 1.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: Apparatus having a string of series-connected memory cells, a plurality of access lines with each access line of the plurality of access lines connected to a control gate of a respective memory cell of the plurality of memory cells, and a controller for access of the string of series-connected memory cells and configured to cause the memory to increase a threshold voltage of a particular memory cell of the string of series-connect memory cells to a voltage level higher than a predetermined pass voltage to be received by a control gate of the particular memory cell during a read operation on the string of series-connected memory cells, and concurrently change a respective data state of each memory cell of a plurality of memory cells of the string of series-connected memory cells.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: Control logic in a memory device causes a first programming pulse of a set of programming pulses associated with a programming algorithm to be applied to a wordline associated with a memory cell to be programmed to a first target voltage level representing a first programming level. The control logic further performs a program verify operation corresponding to the first programming level to determine that a threshold voltage of the memory cell exceeds the first target voltage level. The control logic further causes first data to be stored in a cache, the first data indicating that the threshold voltage of the memory cell exceeds the first target voltage level. The cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the first target voltage level. In view of the second data, a further programming pulse is caused to be applied to the wordline associated with the memory cell at a reduced programming stress level.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: Embodiments of this application disclose a rule detection method, to increase rule anomaly detection coverage. The method in the embodiments of this application includes: determining, based on an obtained first initial priority corresponding to a first rule, an obtained second current priority corresponding to a second rule, and a determined inclusion relationship between the first rule and the second rule, a first current priority corresponding to the first rule; and then determining, based on a relationship between the first initial priority and the first current priority, whether an anomaly occurs on the first rule.

Abstract: This application provides a traffic classification method and apparatus. The method includes: determining, based on distribution characteristics of concerned bits of a plurality of rules in a first rule set, an effective bit corresponding to the first rule set; determining a hash key value of each rule based on a value of the effective bit of each rule in the first rule set, and storing each rule in the first rule set in at least one of S storage units based on the hash key value, where the first rule set is any one of N rule sets, the N rule sets are stored in the S storage units; and when traffic classification is performed, searching for a corresponding rule in each of the S storage units based on a hash key value of a search key.

Abstract: Apparatus having a string of series-connected memory cells, a plurality of access lines with each access line of the plurality of access lines connected to a control gate of a respective memory cell of the plurality of memory cells, and a controller for access of the string of series-connected memory cells and configured to cause the memory to increase a threshold voltage of a particular memory cell of the string of series-connect memory cells to a voltage level higher than a predetermined pass voltage to be received by a control gate of the particular memory cell during a read operation on the string of series-connected memory cells, and concurrently change a respective data state of each memory cell of a plurality of memory cells of the string of series-connected memory cells.