Patents by Inventor Zhengyi Zhang

Zhengyi Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220086126
    Abstract: Embodiments of this application disclose a rule detection method, to increase rule anomaly detection coverage. The method in the embodiments of this application includes: determining, based on an obtained first initial priority corresponding to a first rule, an obtained second current priority corresponding to a second rule, and a determined inclusion relationship between the first rule and the second rule, a first current priority corresponding to the first rule; and then determining, based on a relationship between the first initial priority and the first current priority, whether an anomaly occurs on the first rule.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 17, 2022
    Inventors: Feiran Yang, Jian Zhang, Jing Hu, Zhengyi Zhang, Jun Gong
  • Publication number: 20210409337
    Abstract: This application provides a traffic classification method and apparatus. The method includes: determining, based on distribution characteristics of concerned bits of a plurality of rules in a first rule set, an effective bit corresponding to the first rule set; determining a hash key value of each rule based on a value of the effective bit of each rule in the first rule set, and storing each rule in the first rule set in at least one of S storage units based on the hash key value, where the first rule set is any one of N rule sets, the N rule sets are stored in the S storage units; and when traffic classification is performed, searching for a corresponding rule in each of the S storage units based on a hash key value of a search key.
    Type: Application
    Filed: September 8, 2021
    Publication date: December 30, 2021
    Inventors: Jing HU, Shuzhen TIAN, Zhengyi ZHANG
  • Publication number: 20210366558
    Abstract: Apparatus having a string of series-connected memory cells, a plurality of access lines with each access line of the plurality of access lines connected to a control gate of a respective memory cell of the plurality of memory cells, and a controller for access of the string of series-connected memory cells and configured to cause the memory to increase a threshold voltage of a particular memory cell of the string of series-connect memory cells to a voltage level higher than a predetermined pass voltage to be received by a control gate of the particular memory cell during a read operation on the string of series-connected memory cells, and concurrently change a respective data state of each memory cell of a plurality of memory cells of the string of series-connected memory cells.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 25, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Zhengyi Zhang, Dan Xu, Tomoko Ogura Iwasaki
  • Patent number: 11087851
    Abstract: Apparatus having a string of series-connected memory cells comprising a plurality of principal memory cells and a plurality of dummy memory cells might have a controller configured to cause the apparatus to apply a first programming pulse to a particular dummy memory cell of the plurality of dummy memory cells sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level sufficient to cause the particular dummy memory cell to remain deactivated during a read operation on the string of series-connected memory cells, and to concurrently apply a second programming pulse to each principal memory cell of the plurality of principal memory cell sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Zhengyi Zhang, Dan Xu, Tomoko Ogura Iwasaki
  • Publication number: 20210202013
    Abstract: Apparatus having a string of series-connected memory cells comprising a plurality of principal memory cells and a plurality of dummy memory cells might have a controller configured to cause the apparatus to apply a first programming pulse to a particular dummy memory cell of the plurality of dummy memory cells sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level sufficient to cause the particular dummy memory cell to remain deactivated during a read operation on the string of series-connected memory cells, and to concurrently apply a second programming pulse to each principal memory cell of the plurality of principal memory cell sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells.
    Type: Application
    Filed: June 8, 2020
    Publication date: July 1, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Zhengyi Zhang, Dan Xu, Tomoko Ogura Iwasaki
  • Patent number: 10854300
    Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: December 1, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Vinh Diep, Zhengyi Zhang
  • Publication number: 20200312410
    Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.
    Type: Application
    Filed: June 10, 2020
    Publication date: October 1, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Vinh Diep, Zhengyi Zhang
  • Patent number: 10762973
    Abstract: Program disturb is suppressed during a program recovery phase of a program operation in a memory device. The duration of the recovery phase can be increased when the risk of program disturb is greater due to factors such as temperature, the position of the selected word line, the number of program-erase cycles and the program pulse magnitude. In other approaches, the risk of program disturb is reduced by providing an early ramp down of the voltages of the drain-side word line relative to a ramp down of the voltages of the source-side word lines, providing an early ramp down of the bit line voltage of the inhibited NAND strings relative to the ramp down of the select gate voltage or setting a lower recovery voltage for the source-side word lines relative to the recovery voltage of the drain-side word lines.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: September 1, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Zhengyi Zhang
  • Patent number: 10748627
    Abstract: Techniques for reducing neighbor word line interference (NWI) of memory cells which are formed in a two-tier stack having a lower tier and an upper tier separated by an interface. In one approach, an upward word line programming order is used for a top portion of the top tier, and a downward word line programming order is used for a bottom portion of the top tier and for the bottom tier. Additionally, for memory cells which receive NWI from both adjacent word lines, options include programming fewer bits per cell, performing multi-pass programming and/or use lower verify voltages. Options also include increasing a control gate length of the memory cells and increasing a height of a dielectric region adjacent to the memory cells.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 18, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Yingda Dong, Zhengyi Zhang
  • Patent number: 10706941
    Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 7, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Vinh Diep, Zhengyi Zhang
  • Publication number: 20200202962
    Abstract: Techniques for reducing neighbor word line interference (NWI) of memory cells which are formed in a two-tier stack having a lower tier and an upper tier separated by an interface. In one approach, an upward word line programming order is used for a top portion of the top tier, and a downward word line programming order is used for a bottom portion of the top tier and for the bottom tier. Additionally, for memory cells which receive NWI from both adjacent word lines, options include programming fewer bits per cell, performing multi-pass programming and/or use lower verify voltages. Options also include increasing a control gate length of the memory cells and increasing a height of a dielectric region adjacent to the memory cells.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Yingda Dong, Zhengyi Zhang
  • Patent number: 10446244
    Abstract: Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: October 15, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Vinh Diep, Ching-Huang Lu, Zhengyi Zhang, Yingda Dong
  • Publication number: 20190311772
    Abstract: Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 10, 2019
    Applicant: SanDisk Technologies LLC
    Inventors: Vinh Diep, Ching-Huang Lu, Zhengyi Zhang, Yingda Dong
  • Patent number: 10431313
    Abstract: A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: October 1, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Zhengyi Zhang, Yingda Dong, James Kai, Johann Alsmeier
  • Patent number: 10424387
    Abstract: Apparatuses and techniques are described for programming a memory device with reduced temperature-based changes in the threshold voltage distribution (Vth). Different memory cells can have different values of a temperature coefficient, Tco, and high-Tco memory cells may tend to be at the lower tail of a Vth distribution. The memory cells are programmed using a first set of verify voltages which are temperature-independent. If the temperature at the time of the programming is less than a specified temperature, the high-Tco memory cells are identified and programmed further in a second pass using a second set of verify voltages which are temperature-dependent. Further, the second pass is configured to provide a narrower Vth distribution width than the first program pass. The second pass may use a smaller program pulse step size and/or an elevated bit line voltage.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: September 24, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Zhengyi Zhang, Yingda Dong
  • Patent number: 10297330
    Abstract: Disturbs are reduced during programming and read operations for drain-side memory cells in a string by controlling dummy word line portions separately in selected and unselected sub-blocks. One or more of the dummy word line layers are separated so that they can be driven with different voltages. This allows the channel gradient to be optimized to reduce the likelihood of disturbs. In another aspect, a stack of alternating conductive and dielectric layers is formed in two parts, with lower pillars which comprise select gate transistors, source-side dummy memory cells and data memory cells, below upper pillars which comprise drain-side dummy memory cells and select gate transistors. The upper pillars are relatively narrow to provide a more compact structure. Moreover, the centerline of some upper pillars can be offset from the centerline of corresponding lower pillars to provide room for an isolation region.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: May 21, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Zhengyi Zhang, Henry Chin, Yingda Dong
  • Publication number: 20180358102
    Abstract: Disturbs are reduced during programming and read operations for drain-side memory cells in a string by controlling dummy word line portions separately in selected and unselected sub-blocks. One or more of the dummy word line layers are separated so that they can be driven with different voltages. This allows the channel gradient to be optimized to reduce the likelihood of disturbs. In another aspect, a stack of alternating conductive and dielectric layers is formed in two parts, with lower pillars which comprise select gate transistors, source-side dummy memory cells and data memory cells, below upper pillars which comprise drain-side dummy memory cells and select gate transistors. The upper pillars are relatively narrow to provide a more compact structure. Moreover, the centerline of some upper pillars can be offset from the centerline of corresponding lower pillars to provide room for an isolation region.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 13, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Zhengyi Zhang, Henry Chin, Yingda Dong
  • Patent number: 10134479
    Abstract: A memory system is configured to program different memory cells to different final targets for a common data state based on distance to one or more edges of a word line layer.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: November 20, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhengyi Zhang, Yingda Dong
  • Publication number: 20180308555
    Abstract: A memory system is configured to program different memory cells to different final targets for a common data state based on distance to one or more edges of a word line layer.
    Type: Application
    Filed: April 21, 2017
    Publication date: October 25, 2018
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Zhengyi Zhang, Yingda Dong
  • Publication number: 20180240527
    Abstract: A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.
    Type: Application
    Filed: March 16, 2018
    Publication date: August 23, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Zhengyi Zhang, Yingda Dong, James Kai, Johann Alsmeier