Abstract: Apparatus having a string of series-connected memory cells comprising a plurality of principal memory cells and a plurality of dummy memory cells might have a controller configured to cause the apparatus to apply a first programming pulse to a particular dummy memory cell of the plurality of dummy memory cells sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level sufficient to cause the particular dummy memory cell to remain deactivated during a read operation on the string of series-connected memory cells, and to concurrently apply a second programming pulse to each principal memory cell of the plurality of principal memory cell sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells.

Abstract: Apparatus having a string of series-connected memory cells comprising a plurality of principal memory cells and a plurality of dummy memory cells might have a controller configured to cause the apparatus to apply a first programming pulse to a particular dummy memory cell of the plurality of dummy memory cells sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level sufficient to cause the particular dummy memory cell to remain deactivated during a read operation on the string of series-connected memory cells, and to concurrently apply a second programming pulse to each principal memory cell of the plurality of principal memory cell sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells.

Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.

Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.

Abstract: Program disturb is suppressed during a program recovery phase of a program operation in a memory device. The duration of the recovery phase can be increased when the risk of program disturb is greater due to factors such as temperature, the position of the selected word line, the number of program-erase cycles and the program pulse magnitude. In other approaches, the risk of program disturb is reduced by providing an early ramp down of the voltages of the drain-side word line relative to a ramp down of the voltages of the source-side word lines, providing an early ramp down of the bit line voltage of the inhibited NAND strings relative to the ramp down of the select gate voltage or setting a lower recovery voltage for the source-side word lines relative to the recovery voltage of the drain-side word lines.

Abstract: Techniques for reducing neighbor word line interference (NWI) of memory cells which are formed in a two-tier stack having a lower tier and an upper tier separated by an interface. In one approach, an upward word line programming order is used for a top portion of the top tier, and a downward word line programming order is used for a bottom portion of the top tier and for the bottom tier. Additionally, for memory cells which receive NWI from both adjacent word lines, options include programming fewer bits per cell, performing multi-pass programming and/or use lower verify voltages. Options also include increasing a control gate length of the memory cells and increasing a height of a dielectric region adjacent to the memory cells.

Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.

Abstract: Techniques for reducing neighbor word line interference (NWI) of memory cells which are formed in a two-tier stack having a lower tier and an upper tier separated by an interface. In one approach, an upward word line programming order is used for a top portion of the top tier, and a downward word line programming order is used for a bottom portion of the top tier and for the bottom tier. Additionally, for memory cells which receive NWI from both adjacent word lines, options include programming fewer bits per cell, performing multi-pass programming and/or use lower verify voltages. Options also include increasing a control gate length of the memory cells and increasing a height of a dielectric region adjacent to the memory cells.

Abstract: Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.

Abstract: Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.

Abstract: A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.

Abstract: Apparatuses and techniques are described for programming a memory device with reduced temperature-based changes in the threshold voltage distribution (Vth). Different memory cells can have different values of a temperature coefficient, Tco, and high-Tco memory cells may tend to be at the lower tail of a Vth distribution. The memory cells are programmed using a first set of verify voltages which are temperature-independent. If the temperature at the time of the programming is less than a specified temperature, the high-Tco memory cells are identified and programmed further in a second pass using a second set of verify voltages which are temperature-dependent. Further, the second pass is configured to provide a narrower Vth distribution width than the first program pass. The second pass may use a smaller program pulse step size and/or an elevated bit line voltage.

Abstract: Disturbs are reduced during programming and read operations for drain-side memory cells in a string by controlling dummy word line portions separately in selected and unselected sub-blocks. One or more of the dummy word line layers are separated so that they can be driven with different voltages. This allows the channel gradient to be optimized to reduce the likelihood of disturbs. In another aspect, a stack of alternating conductive and dielectric layers is formed in two parts, with lower pillars which comprise select gate transistors, source-side dummy memory cells and data memory cells, below upper pillars which comprise drain-side dummy memory cells and select gate transistors. The upper pillars are relatively narrow to provide a more compact structure. Moreover, the centerline of some upper pillars can be offset from the centerline of corresponding lower pillars to provide room for an isolation region.

Abstract: Disturbs are reduced during programming and read operations for drain-side memory cells in a string by controlling dummy word line portions separately in selected and unselected sub-blocks. One or more of the dummy word line layers are separated so that they can be driven with different voltages. This allows the channel gradient to be optimized to reduce the likelihood of disturbs. In another aspect, a stack of alternating conductive and dielectric layers is formed in two parts, with lower pillars which comprise select gate transistors, source-side dummy memory cells and data memory cells, below upper pillars which comprise drain-side dummy memory cells and select gate transistors. The upper pillars are relatively narrow to provide a more compact structure. Moreover, the centerline of some upper pillars can be offset from the centerline of corresponding lower pillars to provide room for an isolation region.

Abstract: A memory system is configured to program different memory cells to different final targets for a common data state based on distance to one or more edges of a word line layer.

Abstract: A memory system is configured to program different memory cells to different final targets for a common data state based on distance to one or more edges of a word line layer.

Abstract: A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.

Abstract: Techniques are provided to boost current in channels of memory strings during sensing operations based on a data pattern or a pattern of physical non-uniformities, such as non-uniform channel widths. In one aspect, sense circuits are modified for memory strings which typically store meta data in a high programmed state. A bit line clamping transistor in these sense circuits can be configured with a relatively low threshold voltage, resulting in a relatively high clamping voltage which in turn causes a higher string current during sensing. The lower threshold voltage can be achieved by at least one of a shorter control gate length, a smaller oxide thickness, a lower oxide dielectric constant, or a greater source and/or drain doping concentration. In another aspect, memory strings which expected to typically store high state data are fabricated with a relatively thicker channel and/or greater doping concentration.

Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel of the string is charged up from a source end of the string. However, there is a delay in charging up a drain end of the channel. A voltage detector connected to a bit line detects when a drain end of the channel reaches a reference voltage. When the reference voltage is reached, a voltage of the select gate transistor at the drain end of the string can be floated. This avoids unintentional programming of the select gate transistor which could otherwise occur if the voltage was floated to soon. Also, a substrate voltage may be ramped up to a first detected level before being ramped up to a second, final level.

Abstract: A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.