Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has a first register storing a Hash value pointer, a second register storing a public key pointer, a third register storing a signature pointer, and a fourth register for storage of a verified result. In response to a first elliptic curve cryptographic instruction of an instruction set architecture, the processor reads the Hash value of the data by referring to the first register, obtains the public key by referring to the second register, obtains the digital signature to be verified by referring to the third register, performs a signature verification procedure using the elliptic curve cryptographic algorithm on the Hash value based on the public key and the digital signature to be verified to generate the verified result, and programs the verified result into the fourth register.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has a first register, storing a private key pointer pointing to a private key. In response to a single elliptic curve cryptographic instruction of an instruction set architecture, the processor reads a ciphertext input from a first storage space within a system memory, performing a decryption procedure using the elliptic curve cryptographic algorithm on the ciphertext input based on the private key obtained by referring to the first register to decrypt the ciphertext input and generate a plaintext output, and programming the plaintext output into a second storage space within the system memory.

Abstract: A ray scanning apparatus, including: a conveying device for conveying an object under inspection to pass through a scanning area; a ray source assembly including a plurality of ray source modules arranged around the scanning area on an upper side of the conveying device and fixed in a plane perpendicular to a conveying direction of the object under inspection; and a detector assembly including a plurality of detector sets fixed in a plane perpendicular to the conveying direction of the object under inspection; the detector assembly is located between the ray source assembly and the scanning area in a direction perpendicular to the conveying direction of the object under inspection, the ray source assembly and the detector assembly are arranged to overlap at least partially in the conveying direction of the object under inspection, and the plurality of ray source modules are mounted and detached independently of each other.

Abstract: The present disclosure is directed to double junction tandem perovskite solar cells having a n+/n interconnection layer comprising an ion-doped fullerene layer and a metal oxide layer. In certain embodiments, the metal oxide is SnO2-x (0<x<1). The ion-doped fullerene and metal oxide layers form Ohmic contacts with the wide bandgap and narrow bandgap perovskite sub cells and demonstrate low resistivity and high power conversion efficiencies.

Abstract: The present utility model belongs to the technical field of charging cases, and discloses a light guide structure of an earphone charging case, including a charging case and earphones. A shell of the charging case is provided with a shell light guide element, and the element penetrates the shell. The earphone is provided with a light source. When the earphone is placed in the charging case, light generated by the earphone light source can be transmitted to the shell light guide element, making the guide element emits light. The light guide structure of the earphone charging case use the light source of the earphone directly through optical simulation so as to realize secondary light guide, so that the shell of the charging case emits light, no additional light source is required, costs are reduced, the size of charging case can be effectively reduced, and miniaturization and lightweight can be realized.

Abstract: Provided are a display panel and a display apparatus. The display panel includes a base substrate, a fifth conductive layer, an electrode layer and a pixel defining layer. The electrode layer includes a plurality of electrode portions, at least one of the electrode portions comprises a body portion and a supplemental portion which are connected with each other, and an orthographic projection of the supplemental portion on the base substrate at least partially overlaps with an orthographic projection of a corresponding power line on the base substrate.

Abstract: A genetically engineered bacterium and a preparation method and use thereof are disclosed. The genetically engineered bacteria contain a gene encoding ?-1,2-fucosyltransferase, and a gene encoding a protein tag is connected to the gene encoding ?-1,2-fucosyltransferase; the protein tag is MBP, SUMO1, SUMO2 or TrxA, the amino acid sequence of the MBP is shown in SEQ ID NO: 2, the amino acid sequence of the SUMO1 is shown in SEQ ID NO: 3, the amino acid sequence of the SUMO2 is shown in SEQ ID NO: 4, the amino acid sequence of the TrxA is shown in SEQ ID NO: 5. Fermentation with the genetically engineered bacteria can greatly increase the yield of 2?-fucosyllactose compared to the genetically engineered bacteria that only expresses ?-1,2-fucosyltransferase exogenously, and the yield can be more than doubled in a preferred case.

Abstract: The invention discloses a genetically engineered bacterium and a method for preparing a fucosylated oligosaccharide using the same. The method includes: transferring a fucosyl group of a donor to an oligosaccharide receptor by a fucosyltransferase heterologously expressed in a genetically engineered bacterium; wherein the donor is a nucleotide-activated donor, the fucosyltransferase has ?-1,2-fucosyltransferase activity; wherein, the fucosyltransferase is selected from one or more of the enzymes corresponding to NCBI Accession Numbers WP_109047124.1, RTL12957.1, MBP7103497.1, WP_120175093.1, RYE22506.1, WP_140393075.1 and HJB91111.1. The preparation method of the invention has high yield, greatly improved substrate conversion rate and product conversion rate, and has the potential to be applied to industrial production.

Abstract: The invention discloses a genetically engineered bacterium and its application in the preparation of sialyllactose. The genetically engineered bacterium has an N-acetylneuraminic acid biosynthesis pathway, includes multiple copies of a gene neuB for encoding sialic acid synthase, and the gene neuB is initiated for expression by a strong promoter. Using the genetically engineered bacteria of the invention to produce sialyllactose has the advantages of high yield and low overall cost.

Abstract: The present invention discloses a genetically engineered bacteria, which is E. coli integrated with lysogenic ?DE3, and lacZ gene is completely inactivated, but does not affect exogenous protein expression of the genetically engineered bacteria. The present invention also discloses a method for culturing the genetically engineered bacteria, and a method for preparing human milk oligosaccharides using the same, and use of the genetically engineered bacteria. The genetically engineered bacteria of the present invention can efficiently produce human milk oligosaccharides, such as 2?-fucosyllactose, and have wide industrial application prospects.

Abstract: A ray scanning apparatus for a luggage conveying system. The apparatus includes: a conveying device for conveying an object under inspection to pass through a scanning area of the ray scanning apparatus; and a plurality of scanning beam planes disposed on a plurality of scanning planes arranging in a conveying direction of the object under inspection, each scanning beam plane includes a ray source module and a detector assembly which are arranged opposite to each other, and the ray source module includes a plurality of ray source points for emitting ray beams, wherein the ray source modules of the plurality of scanning beam planes are arranged on lower, left, and right sides of the scanning area respectively.

Abstract: A shift register unit is provided and includes an input circuit, which is connected to first and second signal input terminals and a first node and receives a first level signal, transmits signal of the first signal input terminal to the first node in response to signal of the first signal input terminal and first level signal to the first node in response to signal of the second signal input terminal; a first control sub-circuit connected to first and second nodes and a clock signal terminal and receiving first level signal, which transmits first level signal to the first node in response to signals of the second node and clock signal terminal; a first output sub-circuit connected to first node, clock signal terminal and signal output terminal, which transmits signal of the clock signal terminal to the signal output terminal in response to signal of the first node.

Abstract: Embodiments of the present application provides a ray scanning apparatus, which includes: a conveying device for conveying an object under inspection to pass through a scanning region of the ray scanning apparatus; a ray source assembly including a plurality of ray source modules, each of the ray source modules including at least one ray source point emitting a ray beam; and a detector assembly for detecting rays transmitting through the object under inspection during scanning and including a plurality of detector sets.

Abstract: A ray scanning apparatus, including: a conveying device; a ray source assembly including a plurality of ray source modules arranged around the scanning area in a non-enclosed structure opened on one side of the scanning area; and a detector assembly including a plurality of detector sets arranged around the scanning area in a non-enclosed structure opened on one side of the scanning area, where the opening of the non-enclosed structure of the ray source assembly is opposite to the opening of the non-enclosed structure of the detector assembly, the plurality of detector sets are fixed in a same plane perpendicular to the conveying direction of the object under inspection, and the plurality of ray source modules of the ray source assembly are arranged in a plurality of different planes perpendicular to the conveying direction of the object under inspection.

Abstract: A processor for building a homogeneous dual computing system is shown. The processor has a trusted core, a normal core, and a shared cache. The trusted core has an access right to an isolated storage space of a system memory. The normal core is homogeneous with the trusted core, and is prohibited from accessing the isolated storage space. In response to a cache flush instruction issued by the normal core, the trusted core initiates and executes a second cache write-back instruction that is different from the first cache write-back instruction. According to the second cache write-back instruction, isolated data associated with the isolated storage space and cached in the shared cache is written back to the isolated storage space before being flushed.

Abstract: A processor for building a homogeneous dual computing system is shown. The processor provides two homogeneous cores. One is used as a trusted core and the other is used as a master core. The trusted core has an access right to an isolated storage space of a system memory. The master core is a normal core that is prohibited from accessing the isolated storage space. The trusted core has a first cryptographic module. In response to a reset of the trusted core, the first cryptographic module operates for firmware verification. This is how the trusted core turns on the processor using trusted firmware.

Abstract: A trusted computing technology is shown. An isolated memory stores a security interrupt descriptor table (SIDT) to correspond to security interrupts triggered by security peripherals. A first register of the trusted core stores a first address pointing to the SIDT. A local advanced programmable interrupt controller in the trusted core provides an interrupt arbiter that arbitrates between peripheral interrupts received from the chipset. When producing an arbitration result showing that a target interrupt is a security interrupt, the interrupt arbiter outputs a security interrupt request and a security interrupt vector to trigger the trusted core to search the SIDT indicated by the first register, to get a target security interrupt descriptor for execution of the corresponding interrupt program.

Abstract: A computing system with trusted computing is shown. The processor includes a normal core, and a trusted core for trusted computing. The system memory provides a normal memory, and an isolated memory for trusted computing. The chipset for the communication among the processor, the system memory, and peripherals includes a monitor and records memory protection configuration information. According to the memory protection configuration information, the monitor permits security peripherals to access the isolated memory, and prohibits normal peripherals from accessing the isolated memory.

Abstract: Provided are a pharmaceutical composition comprising a mineralocorticoid receptor antagonist and use thereof. When the pharmaceutical composition is orally administered to a patient having chronic kidney disease in need thereof, the effective and safe AUC ranges from 188 ng*h/mL to 3173 ng*h/mL, with bioavailability of 50% or more in mammals. When the pharmaceutical composition is orally administered at a daily dose of 0.1 to 1.0 mg to treat chronic kidney disease, the AUC is controlled at a safe and effective level.

Abstract: Provided are a pharmaceutical composition comprising a mineralocorticoid receptor antagonist and use thereof. When the pharmaceutical composition is orally administered to a patient having chronic kidney disease in need thereof, the effective and safe AUC ranges from 188 ng*h/mL to 3173 ng*h/mL, with bioavailability of 50% or more in mammals. When the pharmaceutical composition is orally administered at a daily dose of 0.1 to 1.0 mg to treat chronic kidney disease, the AUC is controlled at a safe and effective level.