Abstract: A trusted computing technology is shown. An isolated memory stores a security interrupt descriptor table (SIDT) to correspond to security interrupts triggered by security peripherals. A first register of the trusted core stores a first address pointing to the SIDT. A local advanced programmable interrupt controller in the trusted core provides an interrupt arbiter that arbitrates between peripheral interrupts received from the chipset. When producing an arbitration result showing that a target interrupt is a security interrupt, the interrupt arbiter outputs a security interrupt request and a security interrupt vector to trigger the trusted core to search the SIDT indicated by the first register, to get a target security interrupt descriptor for execution of the corresponding interrupt program.

Abstract: A computing system with trusted computing is shown. The processor includes a normal core, and a trusted core for trusted computing. The system memory provides a normal memory, and an isolated memory for trusted computing. The chipset for the communication among the processor, the system memory, and peripherals includes a monitor and records memory protection configuration information. According to the memory protection configuration information, the monitor permits security peripherals to access the isolated memory, and prohibits normal peripherals from accessing the isolated memory.

Abstract: Disclosed is a sub-Kelvin temperature zone refrigeration mechanism. The sub-Kelvin temperature zone refrigeration mechanism includes a pulse tube refrigeration unit, first pre-cooling heat exchangers, a throttling refrigeration unit, second pre-cooling heat exchangers, an adsorption refrigeration unit, a third pre-cooling heat exchanger and a dilution refrigeration unit. The pulse tube refrigeration unit includes a pulse tube refrigeration part. The throttling refrigeration unit includes a throttling refrigeration part, and the throttling refrigeration part is connected with the adsorption refrigeration unit through the second pre-cooling heat exchangers so as to pre-cool the adsorption refrigeration unit. The adsorption refrigeration unit includes an adsorption refrigeration part, and the adsorption refrigeration part is connected with the dilution refrigeration unit through the third pre-cooling heat exchanger.

Abstract: Provided are a method and apparatus for evaluating a degree of frequency regulation urgency of a generator set, a power system and a storage medium.

Abstract: The present disclosure provides a shift register unit, a driving method, a driving circuit and a display device. The shift register unit includes a first node potential adjustment circuit, a first tank circuit, a second node control circuit, a second tank circuit, a third node control circuit, a first node control circuit, and an output circuit; the first node potential adjustment circuit changes the potential of the first node according to the adjustment clock signal under the control of the potential of the first node; the first tank circuit is used to maintain the potential of the first node; the third node control circuit controls the potential of the third isolation node and the potential of the fourth node; the second node control circuit controls the potential of the second isolation node.

Abstract: Provided are a pharmaceutical composition comprising a mineralocorticoid receptor antagonist and use thereof. When the pharmaceutical composition is orally administered to a patient having chronic kidney disease in need thereof, the effective and safe AUC ranges from 188 ng*h/mL to 3173 ng*h/mL, with bioavailability of 50% or more in mammals. When the pharmaceutical composition is orally administered at a daily dose of 0.1 to 1.0 mg to treat chronic kidney disease, the AUC is controlled at a safe and effective level.

Abstract: Provided are a pharmaceutical composition comprising a mineralocorticoid receptor antagonist and use thereof. When the pharmaceutical composition is orally administered to a patient having chronic kidney disease in need thereof, the effective and safe AUC ranges from 188 ng*h/mL to 3173 ng*h/mL, with bioavailability of 50% or more in mammals. When the pharmaceutical composition is orally administered at a daily dose of 0.1 to 1.0 mg to treat chronic kidney disease, the AUC is controlled at a safe and effective level.

Abstract: An electronic device comprises a first processor, a second processor and a communication interface. The first processor operates according to a first clock, and comprises a first time-stamp counter to count the first clock to obtain a first count value. The second processor operates according to a second clock, and comprises a second time-stamp counter to count the second clock to obtain a second count value. The communication interface is coupled between the first processor and the second processor. The first processor periodically sends the first count value to the second processor through the communication interface. When the second processor receives the first count value, the second processor adds a preset deviation value to the first count value to obtain a synchronization value, resets the second count value, and the sum of the synchronization value and the second count value is read by the second processor.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. Three elliptic curve cryptographic instructions are proposed in the instruction set architecture for key exchange between an initiator and a responder. The initiator device executes the first elliptic curve cryptographic instruction to generate a key pair (rA, RA). In addition to considering the first temporary public key RA, the responder device further takes the second temporary public key RB into consideration when executing the second elliptic curve cryptographic instruction to generate the responder-generated shared key KB. Based on the temporary private key rA, and the temporary public keys RA and RB, the initiator device executes the third elliptic curve cryptographic instruction to generate the initiator-generated shared key KA.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has a first register, storing a public key pointer pointing to a public key. In response to a single elliptic curve cryptographic instruction of an instruction set architecture, the processor reads a plaintext input from a first storage space within a system memory, performing an encryption procedure using the elliptic curve cryptographic algorithm on the plaintext input based on the public key obtained by referring to the first register to encrypt the plaintext input and to generate a ciphertext output, and programming the ciphertext output into a second storage space within the system memory.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has first register storing a Hash value pointer, and a second register, storing a private key pointer. In response to a first elliptic curve cryptographic instruction of an instruction set architecture, the processor reads a first storage space within a system memory by referring to the first register to get a Hash value of the data to be signed, reads a private key by referring to the second register, performs a signature procedure using the elliptic curve cryptographic algorithm on the Hash value based on the private key to generate a digital signature, and programs the digital signature into a second storage space within the system memory.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has a first register, storing a private key pointer pointing to a private key. In response to a single elliptic curve cryptographic instruction of an instruction set architecture, the processor reads a ciphertext input from a first storage space within a system memory, performing a decryption procedure using the elliptic curve cryptographic algorithm on the ciphertext input based on the private key obtained by referring to the first register to decrypt the ciphertext input and generate a plaintext output, and programming the plaintext output into a second storage space within the system memory.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has a first register storing a Hash value pointer, a second register storing a public key pointer, a third register storing a signature pointer, and a fourth register for storage of a verified result. In response to a first elliptic curve cryptographic instruction of an instruction set architecture, the processor reads the Hash value of the data by referring to the first register, obtains the public key by referring to the second register, obtains the digital signature to be verified by referring to the third register, performs a signature verification procedure using the elliptic curve cryptographic algorithm on the Hash value based on the public key and the digital signature to be verified to generate the verified result, and programs the verified result into the fourth register.

Abstract: A processor with a block cipher algorithm and a data encryption and decryption method operated by the processor are shown. The processor uses a register to store an input key pointer pointing to an input key. In response to one single block cipher instruction of an instruction set architecture (ISA), the processor obtains input data from a first system memory area, performs the block cipher algorithm on the input data based on the input key indicated by the input key pointer stored in the register to encrypt or decrypt the input data to generate output data, and stores the output data in a second system memory area, or an internal storage area within the processor.

Abstract: A processor with a Hash cryptographic algorithm and a data processing method are shown. In response to one single Hash cryptographic instruction of an instruction set architecture, the processor reads a first storage space within a system memory to obtain an input message of a limited length, and processes the input message in accordance with the Hash cryptographic algorithm to generate a final Hash value of a specific length.

Abstract: The present invention provides a novel antibiotic compound represented by the following formula (I), a pharmaceutically acceptable salt thereof, an ester thereof, a prodrug thereof, a solvate thereof, or a deuterated analog thereof, or a stereoisomer thereof. The compound of the present invention exhibits excellent antibacterial activity, especially against Gram bacteria. wherein each group is defined as in the description.

Abstract: In one aspect, the present invention features a method of inhibiting proliferation and/or reducing survival of a cell comprising a GNAQ polynucleotide or polypeptide having a R183Q or Q209L mutation, comprising contacting the cell with puromycin or a puromycin analog, thereby inhibiting proliferation and/or reducing survival of the cell. In another aspect, a method of treating a vascular malformation or related condition in a subject, comprising administering to the subject an effective amount of puromycin or a puromycin analog is featured.

Abstract: A data processing method includes the following steps: a processor receives a symmetric wrapping key, and when an application needs to use a user private key, the processor executes an encryption and decryption instruction in a hardware-acceleration instruction-set. The encryption and decryption instruction is configured to apply the symmetric wrapping key to decrypt a wrapped private key that corresponds to the application to obtain the user private key. In addition, the symmetric wrapping key is stored in a model specific register of the processor.

Abstract: The present application discloses a process for preparing a fused tricyclic compound and an intermediate thereof, specifically relates to a process for preparing a (3S,3aR)-3-cyclopentyl-3,3a,4,5-tetrahydro-2H-pyrazolo[3,4-f]quinoline compound, intermediates in said process, and methods for preparing said intermediates.

Abstract: An electronic device comprises a first processor, a second processor and a communication interface. The first processor operates according to a first clock, and comprises a first time-stamp counter to count the first clock to obtain a first count value. The second processor operates according to a second clock, and comprises a second time-stamp counter to count the second clock to obtain a second count value. The communication interface is coupled between the first processor and the second processor. The first processor periodically sends the first count value to the second processor through the communication interface. When the second processor receives the first count value, the second processor adds a preset deviation value to the first count value to obtain a synchronization value, resets the second count value, and the sum of the synchronization value and the second count value is read by the second processor.