Abstract: A circuit for converting first and second differential input signals into an output signal is provided with a first differential input stage comprising first and second inputs for receiving the first differential input signal and comprising first and second outputs and with a second differential input stage comprising third and fourth inputs for receiving the second differential input signal and comprising third and fourth outputs and with an output stage comprising a first terminal connected to the first output that is further connected to the third output and comprising a second terminal connected to the second output that is further connected to the fourth output and comprising a third terminal for providing the output signal, to avoid complex operational amplifiers. The differential input stages comprise two pairs of transistors and the output stage comprises a current mirror with a third pair of transistors.

Abstract: A low dropout (LDO) voltage regulator comprises a regulating element (10) having an input (12), an output (14) and a control terminal (16), an error amplifier (22) having a non-inverting input (28) coupled to a node (30) of a potential divider sampling an output voltage (Vo) at the output (14) of the regulating element, an inverting input (24) coupled to a source (26) of a reference voltage (Vref) and an output coupled to the control terminal (16) of the regulating element, and means for generating an internal zero. The means for generating an internal zero comprises an operational amplifier (52) having a non-inverting input (54) coupled to the node (30) of the potential divider, an output (58) coupled to the non-inverting input (28) of the error amplifier, a resistive element (60) connected between the output and an inverting input (56) of the operational amplifier and a capacitive element (62) coupled between the inverting input of the operational amplifier and the source of reference voltage.

Abstract: A switching regulator having first and second power switches. The first power switch has at least two transistors connected in series, the transistors having a first maximum voltage across their terminals which is less than the input voltage of the regulator. The transistors have at least a first node at the point where they are connected, and a first control circuit controls the voltage at the first node so that the voltages across the terminals of the transistors of the first power switch do not exceed the first maximum voltage. The second power switch also has at least two transistors connected in series, the transistors having a maximum voltage across their terminals that is less than the input voltage. The transistors have at least a second node at the point where they are connected, and a second control circuit controls the voltage at the second node so that the voltages across the terminals of the transistors of the second power switch do not exceed the second maximum voltage.

Abstract: An integrated oscillator (10), for an integrated circuit, comprises i) first (CI1) and second (CI2) compensated inverters mounted in series and each comprising first (PI11;PI21) and second (PI12;PI22) plain inverters mounted in parallel and comprising transistors having channel lengths respectively shorter and longer than an optimal channel length, the first compensated inverter (CI1) having input and output terminals respectively connected to first (N1) and second (N2) nodes and the second compensated inverter (CI2) having input and output terminals respectively connected to the second node (N2) and to a third node (N3), ii) a resistor (R) having a chosen resistance value and comprising first and second terminals connected respectively to the first (N1) and second (N2) nodes, and iii) a capacitor (C) comprising first and second terminals connected respectively to the first (N1) and third (N3) nodes, and having a chosen capacitance value to charge and discharge oneself in order to periodically deliver a clock

Abstract: A continuous-time filter system comprises a master control unit and a slave unit with one or more slave filters. The master control unit includes an integrator having circuit elements which match those elements of the slave filter that define the slave filter's time constant. The master control unit further includes a voltage comparator connected to an output of the integrator, the voltage comparator providing an output frequency signal, and a phase frequency comparator providing a control signal as an output signal, the phase frequency comparator receiving said output frequency signal and a reference frequency signal as input signals. The slave unit includes said at least one slave filter, the slave filter having a control signal input for receiving said control signal thus allowing to calibrate the slave filter's transfer function by influencing the slave filter's time constant.

Abstract: An electronic device has at least one integrated circuit with at least one MOS transistor. An adaptive analog biasing unit is configured to provide an adaptive biasing current for the at least one MOS transistor biased in the saturation region. The adaptive analog biasing unit (AAB) may be on the same chip together with the integrated circuit and may comprise a process monitor unit configure to extract a device parameter of the integrated circuits and a calculation unit configured to generate a bias current based on the output of the process monitor unit. The bias current generated by the calculation unit may be inversely proportional to the extracted device parameter.

Abstract: A semi-adaptive voltage scaling method and device for determining minimal supply voltages for digital electronic semiconductor circuitry, e.g., microprocessors, of electronic devices under production testing and “real” operating conditions. The SAVS operates in a closed-loop during a production test phase of the circuitry and in an open-loop mode in an application (operation) phase of the semiconductor circuitry. During production testing, a lowermost level of the supply voltage for the semiconductor circuitry is determined at one single defined temperature at which operating specifications of the circuit are met. The lowermost level is stored in a dedicated electronic memory of the circuitry together with temperature dependent parameters. Afterwards, when the digital electronic circuitry is operated in a “real” application, e.g.

Abstract: A switchable integrated electronic device includes at least three elements r1 . . . r14, s1 . . . s14 series coupled in a chain between a first port and a second port and includes a node between successive elements r1 . . . r14, s1 . . . s14 of the chain. There is a switch means for coupling a selectable one of the nodes to a third port. If successive elements r1 . . . r14, s1 . . . s14 in the chain are denoted ri, i=1 to N, and if adjacent positions occupied by the elements are numbered consecutively 1 to N, then element ri occupies position ? N + 1 2 ? + ( - 1 ) i · 2 · ? i 2 ? ? ? ? for ? ? i = 1 ? ? to ? ? ? N 2 ? and position ? N + 1 2 ? + ( - 1 ) i · ( 2 · ? N - i 2 ? + 1 ) ? ? for ? ? i = ? N 2 ? + 1 ? ? to ? ? N .

Abstract: In a transmission network system in which a path is set between a transmission node and a receiving node and which transmits a transmission signal between the nodes, crossconnect settings of the nodes are enabled while personal settings are minimized. A transmission node has a first path-setting-receiving section; transmission-path-setting change sections; and change insertion sections which report information about a change in path setting received by said path-setting-receiving section by inserting the information into a transmission signal to be transmitted from the node to a receiving node. The receiving node has a second path-setting-receiving section and receiving-path-setting change sections for changing path settings of the node on the basis of the information about a change in path setting.

Abstract: A circuit (1) for converting first and second differential input signals into an output signal is provided with a first differential input stage (10) comprising first and second inputs (11,12) for receiving the first differential input signal and comprising first and second outputs (13,14) and with a second differential input stage (20) comprising third and fourth inputs (21,22) for receiving the second differential input signal and comprising third and fourth outputs (23,24) and with an output stage (30) comprising a first terminal (31) connected to the first output (11) that is further connected to the third output (21) and comprising a second terminal (32) connected to the second output (12) that is further connected to the fourth output (22) and comprising a third terminal (33) for providing the output signal, to avoid complex operational amplifiers.

Abstract: In a transmission network system in which a path is set between a transmission node and a receiving node and which transmits a transmission signal between the nodes, crossconnect settings of the nodes are enabled while personal settings are minimized. A transmission node has a first path-setting-receiving section; transmission-path-setting change sections; and change insertion sections which report information about a change in path setting received by said path-setting-receiving section by inserting the information into a transmission signal to be transmitted from the node to a receiving node. The receiving node has a second path-setting-receiving section and receiving-path-setting change sections for changing path settings of the node on the basis of the information about a change in path setting.

Abstract: The present invention concerns a reference voltage generator (40) that provides a reference voltage (Vref new). The voltage generator (30) is operated at a supply voltage (Vdd) being lower than the Silicon bandgap voltage. It comprises a MOSFET transistor (MN; MN3; MP4; MP7) serving as transconductor (Gptat). An input node for feeding a drain current (Iptat) into the drain of said MOSFET transistor (MN; MN3; MP4; MP7) is provided and an output node is connected to the drain and gate of said MOSFET transistor (MN; MN3; MP4; MP7). A current generator (42) allows the MOSFET transistor (MN; MN3; MP4; MP7) to be operated in a specific mode where the drain current (Iptat) has a positive temperature coefficient (?ptat) and the transconductor (Gptat) has a negative temperature coefficient (?ptat).

Abstract: A receiver includes a mixer with a first input, a second input and one output. An input signal (SRF(t)), which has a high frequency component fRF, is applied to the first input, and a local oscillator signal (SLOnew(t)) is applied to the second input of the mixer. The local oscillator signal (SLOnew(t)) is generated by a source and the local oscillator signal (SLOnew(t)) has a frequency component with a frequency fLO. The frequency fLOnew is at least three times lower than the frequency fRF of the input signal (SRF(t)). The mixer down-converts the input signal (SRF(t)) to a lower frequency band.

Abstract: An integrated oscillator (10), for an integrated circuit, comprises i) first (CI1) and second (CI2) compensated inverters mounted in series and each comprising first (PI11;PI21) and second (PI12;PI22) plain inverters mounted in parallel and comprising transistors having channel lengths respectively shorter and longer than an optimal channel length, the first compensated inverter (CI1) having input and output terminals respectively connected to first (N1) and second (N2) nodes and the second compensated inverter (CI2) having input and output terminals respectively connected to the second node (N2) and to a third node (N3), ii) a resistor (R) having a chosen resistance value and comprising first and second terminals connected respectively to the first (N1) and second (N2) nodes, and iii) a capacitor (C) comprising first and second terminals connected respectively to the first (N1) and third (N3) nodes, and having a chosen capacitance value to charge and discharge oneself in order to periodically deliver a clock

Abstract: A linear transconductor (LT), for instance for a one-cycle controller (OC), comprises i) an operational amplifier (OA) having non-inverting (+) and inverting (?) inputs, a power supply input intended to be connected to a DC voltage (VBAT), and an output (OO), ii) a voltage divider means (R1,R2) comprising a first terminal defining a transconductor non-inverting input (Vin+) and intended to be connected to a first voltage (Vx), and a second terminal connected to the operational amplifier inverting input (?), iii) a resistor (R3) comprising a first terminal defining a transconductor inverting input (Vin?) intended to be connected to a second voltage and a second terminal connected to the operational amplifier non-inverting input (+), v) first (T1) and second (T2) matched transistors having respective sources connected together and to the operational amplifier power supply input, respective common gates connected to the operational amplifier output (OO), and respective drains, the drain of the first transistor (

Abstract: The present invention concerns a reference voltage generator (40) that provides a reference voltage (Vref new). The voltage generator (30) is operated at a supply voltage (Vdd) being lower than the Silicon bandgap voltage. It comprises a MOSFET transistor (MN; MN3; MP4; MP7) serving as transconductor (Gptat). An input node for feeding a drain current (Iptat) into the drain of said MOSFET transistor (MN; MN3; MP4; MP7) is provided and an output node is connected to the drain and gate of said MOSFET transistor (MN; MN3; MP4; MP7). A current generator (42) allows the MOSFET transistor (MN; MN3; MP4; MP7) to be operated in a specific mode where the drain current (Iptat) has a positive temperature coefficient (?ptat) and the transconductor (Gptat) has a negative temperature coefficient (?ptat).

Abstract: A switching regulator having first and second power switches. The first power switch has at least two transistors connected in series, the transistors having a first maximum voltage across their terminals which is less than the input voltage of the regulator. The transistors have at least a first node at the point where they are connected, and a first control circuit controls the voltage at the first node so that the voltages across the terminals of the transistors of the first power switch do not exceed the first maximum voltage. The second power switch also has at least two transistors connected in series, the transistors having a maximum voltage across their terminals that is less than the input voltage. The transistors have at least a second node at the point where they are connected, and a second control circuit controls the voltage at the second node so that the voltages across the terminals of the transistors of the second power switch do not exceed the second maximum voltage.

Abstract: A continuous-time filter system comprises a master control unit and a slave unit with one or more slave filters. The master control unit includes an integrator having circuit elements which match those elements of the slave filter that define the slave filter's time constant. The master control unit further includes a voltage comparator connected to an output of the integrator, the voltage comparator providing an output frequency signal, and a phase frequency comparator providing a control signal as an output signal, the phase frequency comparator receiving said output frequency signal and a reference frequency signal as input signals. The slave unit includes said at least one slave filter, the slave filter having a control signal input for receiving said control signal thus allowing to calibrate the slave filter's transfer function by influencing the slave filter's time constant.

Abstract: Apparatus (20) for generating a sine shaped output signal at an output (Sn, Sp). The apparatus (20) comprises a first transistors (M1) and a second transistor (M2) being arranged as differential pair (22). The differential pair (22) has two input nodes (Tp, Tn) allowing a triangular input signal (Vin(t)) with a given amplitude (A) to be applied between a gate (Tp) of the first transistor (M1) and a gate (Tn) of the second transistor (M2). The differential pair (22) further comprises a node (X) where a source of the first transistor (M1) and a source of the second transistor (M2) is connected. The sine wave shaped signal is provided between a drain (Sp) of the first transistor (M1) and a drain (Sn) of the second transistor (M2). A current mirror (21) is employed for feeding a predefined tail current (Iss) into/out of the node (X) of said differential pair (22).

Abstract: Continuous-time filter system with self-calibration means. The system comprises a master control unit (36) and a slave unit with one or more slave filters (27.1-27.n). The master control unit (36) comprises an integrator (30) having circuit elements (33, C) which match those elements of the slave filter (27.1-27.n) that define the slave filter's time constant (?). Furthermore, the master control unit (36) comprises a voltage comparator (35) connected to an output (34) of the integrator (30), the voltage comparator (35) providing an output frequency signal (fcom), and a phase frequency comparator (PFC; 28) providing a control signal (?) as output signal, the phase frequency comparator (PFC; 28) receiving said output frequency signal (fcom) and a reference frequency signal (fref) as input signals. The slave unit comprises said at least one slave filter (27.1-27.n), the slave filter (27.1-27.