Abstract: A receiver apparatus including a main input for receiving the input signal and a first standard mixer having a first mixer input, a first local oscillator input, and a first mixer output. The first mixer input is connected to the main input and the first local oscillator input is connected to a source that provides a first local oscillator signal having a frequency close to or equal to the carrier frequency. The apparatus further including a second mixer with a second mixer input, a second local oscillator input, and a second mixer output. The second mixer input is connected to the main input and the second local oscillator input is connected to a source that provides a second local oscillator signal with an undesired sideband frequency. There are circuit for super-positioning the first output signal and the second output signal. The first local oscillator signal and the second local oscillator signal are square-wave signals.

Abstract: Apparatus (1) for continuous-time application, comprising an operational amplifier (2) and a self-zeroing control unit (3) for reducing an offset of the operational amplifier (2). The self-zeroing control unit (3) provides for a self zeroing operation mode and a normal operation mode. It comprises a comparator (6), a successive approximation register (7), and a digital-to-analog converter (8).

Abstract: An operational amplifier includes a current provider that introduces an additional current Ic to an internal node A of the operational amplifier for reducing the output offset voltage of the operational amplifier.

Abstract: Apparatus (1) for continuous-time application, comprising an operational amplifier (2) and a self-zeroing control unit (3) for reducing an offset of the operational amplifier (2). The self-zeroing control unit (3) provides for a self zeroing operation mode and a normal operation mode. It comprises a comparator (6), a successive approximation register (7), and a digital-to-analog converter (8).

Abstract: Receiver (20) comprising a mixer (23) with a first input, a second input and one output. An input signal (SRF(t)) comprising a high frequency component fRF is applied to the first input, and a local oscillator signal (SLOnew(t)) is applied to the second input of the mixer (23). The local oscillator signal (SLOnew(t)) is generated by a source (30) and the local oscillator signal (SLOnew(t)) has a frequency component with a frequency fLo11. The frequency fLOnew is at least three times lower than the frequency fRF of the input signal (SRF(t)). The mixer (23) provides for a down-conversion of the input signal (SRF(t)) to a lower frequency band.

Abstract: Apparatus (20) for generating a sine shaped output signal at an output (Sn, Sp). The apparatus (20) comprises a first transistors (M1) and a second transistor (M2) being arranged as differential pair (22). The differential pair (22) has two input nodes (Tp, Tn) allowing a triangular input signal (Vin(t)) with a given amplitude (A) to be applied between a gate (Tp) of the first transistor (M1) and a gate (Tn) of the second transistor (M2). The differential pair (22) further comprises a node (X) where a source of the first transistor (M1) and a source of the second transistor (M2) is connected. The sine wave shaped signal is provided between a drain (Sp) of the first transistor (M1) and a drain (Sn) of the second transistor (M2). A current mirror (21) is employed for feeding a predefined tail current (Iss) into/out of the node (X) of said differential pair (22).

Abstract: Circuit comprising a noise suppressing circuitry (40) having an input (42) for a first voltage (VDD) and an output (43) for providing a supply voltage (VDDfiltered). The circuit further comprises a MOSFET-based switch (41) with a MOSFET (MP) being situated in a well, whereby a supply voltage (VDDfiltered) is applied to the well (67). The first voltage (VDD) is a global voltage used elsewhere in the same circuit, and the supply voltage (VDDfiltered) is less-noisy than the first voltage (VDD).

Abstract: An apparatus for generating an output signal whose frequency is lower than the frequency of an input signal is disclosed. The apparatus includes a chain of frequency dividing cells where each cell has a definable division ratio. Furthermore, the frequency dividing cells include a clock input for receiving an input clock, a divided clock output for providing an output clock to a subsequent frequency dividing cell, a mode control input for receiving a mode control input signal from the subsequent frequency dividing cell, and a mode control output for providing a mode control output signal to a preceding frequency dividing cell. The apparatus may further includes a logic network having one or more inputs where each input is connected to a mode control input of one of the frequency dividing cells.

Abstract: Apparatus (40) for processing an input signal (SRF (t)) with a carrier frequency (?RF) defining a desired band and at least a sideband being defined by a side-band frequency (n?LO) that is higher than the carrier frequency (?RF). The apparatus (40) comprises a main input (50) for receiving said input signal (SRF (t)) and a first standard mixer (41) having a first mixer input (44), a first local oscillator input (47), and a first mixer output (A). The first mixer input (44) is connected to the main input (50) and the first local oscillator input (47) is connected to a source that provides a first local oscillator signal (LO1) having a frequency (?LO). This frequency (?LO) is close to or equal to the carrier frequency (?RF). The first standard mixer (41) performs a multiplication of the input signal (SRF (t)) and the first local oscillator signal (LO1) to provide a first output signal (SA (t)) at the first mixer output (A).

Abstract: Continuous-time filter system with self-calibrafon means. The system comprises a master control unit (36) and a slave unit with one or more slave filters (27.1-27.n). The master control unit (36) comprises an integrator (30) having circuit elements (33, C) which match those elements of the slave filter (27.1-27.n) that define the slave filter's time constant (?). Furthermore, the master control unit (36) comprises a voltage comparator (35) connected to an output (34) of the integrator (30), the voltage comparator (35) providing an output frequency signal (fcom), and a phase frequency comparator (PFC; 28) providing a control signal (?) as output signal, the phase frequency comparator (PFC; 28) receiving said output frequency signal (fcom) and a reference frequency signal (fref) as input signals. The slave unit comprises said at least one slave filter (27.1-27.n), the slave filter (27.1-27.

Abstract: The invention relates to an operational amplifier. In order to enable an improved reduction of the output offset voltage of the operational amplifier, the operational amplifier comprises means S, T for introducing an additional current Ic to an internal node A of the operational amplifier for reducing the output offset voltage of the operational amplifier. The invention relates equally to a method for reducing the output offset voltage of an operational amplifier. This method comprises introducing an additional current Ic to an internal node A of the operational amplifier.

Abstract: In a transmission network system in which a path is set between a transmission node and a receiving node and which transmits a transmission signal between the nodes, crossconnect settings of the nodes are enabled while personal settings are minimized. A transmission node has a first path-setting-receiving section; transmission-path-setting change sections; and change insertion sections which report information about a change in path setting received by said path-setting-receiving section by inserting the information into a transmission signal to be transmitted from the node to a receiving node. The receiving node has a second path-setting-receiving section and receiving-path-setting change sections for changing path settings of the node on the basis of the information about a change in path setting.

Abstract: Circuit comprising a noise suppressing circuitry (40) having an input (42) for a first voltage (VDD) and an output (43) for providing a supply voltage (VDDfiltered). The circuit further comprises a MOSFET-based switch (41) with a MOSFET (MP) being situated in a well, whereby a supply voltage (VDDfiltered) is applied to the well (67). The first voltage (VDD) is a global voltage used elsewhere in the same circuit, and the supply voltage (VDDfiltered) is less-noisy than the first voltage (VDD).

Abstract: A voltage level detection circuit (1) with a threshold level, which is dependent on the manufacturing process. The circuit comprises a first current generator (4), which generates a monitoring current (IM) derived from the voltage (VM) to be monitored. This monitoring current (IM) is compared with a reference current (Iref1). A switchable reference current (Iref2) provides for hysteresis. The first current generator (4) comprises an element, the resistance of which depends on the manufacturing process.

Abstract: A circuit generates an output signal whose frequency is lower than the frequency of an input signal. In an example embodiment, there is a chain of frequency dividing cells. Each of the frequency dividing cells has a pre-defined division ratio and a clock input for receiving an input clock, a divided clock output for providing an output clock to a subsequent frequency dividing cell, a mode control input for receiving a mode control input signal from the subsequent frequency dividing cell, and a mode control output for providing a mode control output signal to a preceding frequency dividing cell. Further included are a latch for altering the division ratio of each of the frequency dividing cells and D-Flip-Flop circuitry having two latches. A first signal clocks the first latch and a second signal clocks the second latch, whereby the frequency of the first signal is lower than the frequency of the second signal.

Abstract: Apparatus (50) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK1, fvco). The apparatus (50) comprises a chain of frequency dividing cells (51-56), wherein each of the frequency dividing cells (51-56) has a definable division ratio (DR) and comprises:—a clock input (CKi) for receiving an input clock (CKin);—a divided clock output (CKi+1) for providing an output clock (CKout) to a subsequent frequency dividing cell;—a mode control input (MDi) for receiving a mode control input signal (MDin) from the subsequent frequency dividing cell; and—a mode control output for providing a mode control output signal (MDout) to a preceding frequency dividing cell. The apparatus (50) further comprises a logic network (58) having m inputs. Each of the m inputs is connected to a mode control input (MDi, MDi+1, MDi+2) of one of the m consecutive frequency dividing cells (51-54).

Abstract: Apparatus (70) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK1). The apparatus (70) comprises a chain of frequency dividing cells (71-76), wherein each of the frequency dividing cells (71-76) has a pre-defined division ratio and comprises a clock input (CKi) for receiving an input clock (CKin); a divided clock output (CKi+1) for providing an output clock (CKout) to a subsequent frequency dividing cell; a mode control input (MDi) for receiving a mode control input signal (MDin) from the subsequent frequency dividing cell; and a mode control output for providing a mode control output signal (MDout) to a preceding frequency dividing cell. The apparatus further comprises a latch (77) for altering the division ratio and—a D-Flip-Flop (50) circuitry with two latches (51, 52).

Abstract: Apparatus including a frequency dividing cell (42) with a prescaler logic, an end-of-cycle logic, a clock input for receiving an input clock (CKin) with frequency fn, a clock output for providing an output clock (CKout) with frequency fm to a subsequent cell (43), a mode control input for receiving a mode control input signal (MDin) from the subsequent cell (43), and a mode control output for providing a mode control output signal (MDout) to a preceding cell (41). The end-of-cycle logic of the frequency dividing cell (42) has a switchable tail current source. This switchable tail current source allows the biasing current of the end-of-cycle logic to be switched off in to save power.

Abstract: A nanocrystal cerium zirconium composite oxide and its preparation and application are disclosed. The nanocrystal cerium zirconium composite oxide of the present invention comprises 4-98% by weight of CeO2 and 1-95% by weight of ZrO2, the crystalline particle size thereof is 100 nm or less, and the ignition loss thereof after igniting at 900° C. for one hour is smaller than 5%.

Abstract: An electronic device which includes a periodic signal generator (12) and a frequency multiplier circuit (14) for multiplying the frequency of the periodic signal. The multiplier circuit is formed on the basis of an EXCLUSIVE-OR gate (20), which receives the periodic signal, and a frequency divider circuit (22) connected between the output and an input of the gate. From this divider circuit it is possible to derive in a very simple way quadrature signals, which makes it feasible to perform a modulation of the type known as “zero demodulation”. The multiplier circuit can operate in accordance with CML technology (Current Mode Logic).