Patents by Inventor Zhenlei Shen

Zhenlei Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210304826
    Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: Zhengang Chen, Sai Krishna Mylavarapu, Zhenlei Shen, Tingjun Xie, Charles S. Kwong
  • Publication number: 20210295900
    Abstract: A media management operation can be performed at a memory sub-system at a current frequency. An operating characteristic associated with the memory sub-system can be identified. The operating characteristic can reflect at least one of a write count, a bit error rate, or a read-retry trigger rate. A determination can be made as to whether the identified operating characteristic satisfies an operating characteristic criterion. In response to determining that the operating characteristic satisfies the characteristic criterion, the media management operation can be performed at a different frequency relative to the current frequency.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Tingjun Xie, Seungjune Jeon, Zhengang Chen, Zhenlei Shen, Charles See Yeung Kwong
  • Patent number: 11056166
    Abstract: A refresh operation can be performed at a memory sub-system The refresh operation can performed at a current frequency. A write count associated with the memory sub-system can be received. A determination can be made as to whether the write count associated with the memory sub-system satisfies a write count threshold. In response to determining that the write count associated with the memory sub-system satisfies the write count threshold, the refresh operation can be performed at an increased frequency relative to the current frequency.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tingjun Xie, Seungjune Jeon, Zhengang Chen, Zhenlei Shen, Charles See Yeung Kwong
  • Publication number: 20210183454
    Abstract: A request to read data at the memory device is received. A first read operation is performed to read the data at the memory device using a first read threshold voltage. The data read at the memory device using the first read threshold voltage is determined to be associated with a first unsuccessful correction of an error. Responsive to determining that the data read at the memory device using the first read threshold voltage is associated with the first unsuccessful correction of the error, a second read threshold voltage is stored at a register to replace a preread threshold voltage previously stored at the register that is associated with the memory device. The first preread threshold voltage was previously used to perform a preread operation at the memory device. A second read operation to read the data at the memory device is performed using the second read threshold voltage.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 17, 2021
    Inventors: Seungjune Jeon, Zhenming Zhou, Zhenlei Shen
  • Patent number: 11037637
    Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device performs an error recovery flow (ERF) to recover a unit of data comprising data and a write timestamp indicating when the unit of data was written. The processing device determines whether to perform a defect detection operation to detect a defect in the memory component using a bit error rate (BER), corresponding to the read operation, and the write timestamp in the unit of data. The processing device initiates the defect detection operation responsive to the BER condition not being expected for the calculated W2R (based on the write timestamp). The processing device can use an ERF condition and the write timestamp to determine whether to perform the defect detection operation. The processing device initiates the defect detection operation responsive to the ERF condition not being expected the calculated W2R (based on the write timestamp).
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: June 15, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Zhengang Chen, Sai Krishna Mylavarapu, Zhenlei Shen, Tingjun Xie, Charles S. Kwong
  • Patent number: 10950315
    Abstract: A request to read data at the memory device is received. A first read operation is performed to read the data at the memory device using a first read threshold voltage. The data read at the memory device using the first read threshold voltage is determined to be associated with a first unsuccessful correction of an error. Responsive to determining that the data read at the memory device using the first read threshold voltage is associated with the first unsuccessful correction of the error, a second read threshold voltage is stored at a register to replace a preread threshold voltage previously stored at the register that is associated with the memory device. The first preread threshold voltage was previously used to perform a preread operation at the memory device. A second read operation to read the data at the memory device is performed using the second read threshold voltage.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 16, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Seungjune Jeon, Zhenming Zhou, Zhenlei Shen
  • Publication number: 20210064279
    Abstract: A processing device in a memory sub-system initiates read operations on each of a plurality of segments in a first region of the memory device during a first time interval, wherein at least a subset of the plurality of segments in the first region of the memory device are storing host data. The processing device further receives, as a result of at least one read operation, at least one data signal from a corresponding one of the plurality of segments in the first region of the memory device, and performs a signal calibration operation using the at least one data signal to synchronize one or more relevant signals with a reference clock signal used by the processing device.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 4, 2021
    Inventors: Tingjun Xie, Zhenming Zhou, Zhenlei Shen, Chih-Kuo Kao
  • Publication number: 20210034291
    Abstract: A request to write data at the memory component is received. Responsive to receiving the request to write the data at the memory component, a random value is determined. A first write operation mode from multiple write operations modes is selected based on the random value. A write operation to write the data at the memory component is performed in accordance with the first write operation mode.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Zhenlei Shen, Fangfang Zhu, Tingjun Xie, Jiangli Zhu
  • Publication number: 20210020229
    Abstract: A refresh operation can be performed at a memory sub-system The refresh operation can performed at a current frequency. A write count associated with the memory sub-system can be received. A determination can be made as to whether the write count associated with the memory sub-system satisfies a write count threshold. In response to determining that the write count associated with the memory sub-system satisfies the write count threshold, the refresh operation can be performed at an increased frequency relative to the current frequency.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Inventors: Tingjun Xie, Seungjune Jeon, Zhengang Chen, Zhenlei Shen, Charles See Yeung Kwong
  • Publication number: 20210011769
    Abstract: An indication that an allocation unit of a memory sub-system has become unmapped can be received. In response to receiving the indication that the allocation unit of the memory sub-system has become unmapped, the allocation unit can be programmed with a data pattern. Data to be written to the unmapped allocation unit can be received. A write operation can be performed to program the received data at the unmapped allocation unit by using a read voltage that is based on the data pattern.
    Type: Application
    Filed: July 12, 2019
    Publication date: January 14, 2021
    Inventors: Tingjun Xie, Zhengang Chen, Zhenlei Shen
  • Publication number: 20210012845
    Abstract: A system includes a plurality of memory devices and a processing device (e.g., a controller), operatively coupled to the plurality of memory devices. The processing device is to detect a power-on of the system and determine a read-retry trigger rate (TR) of a subset of codewords of the plurality of memory devices during a time interval after an initialization of the memory component. The processing device is further to determine whether the TR satisfies a threshold criterion. In response to the TR not satisfying the threshold criterion, the processing device is to initialize a full-memory refresh of the plurality of memory devices.
    Type: Application
    Filed: July 12, 2019
    Publication date: January 14, 2021
    Inventors: Tingjun Xie, Zhenlei Shen, Zhenming Zhou
  • Publication number: 20200185045
    Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device performs an error recovery flow (ERF) to recover a unit of data comprising data and a write timestamp indicating when the unit of data was written. The processing device determines whether to perform a defect detection operation to detect a defect in the memory component using a bit error rate (BER), corresponding to the read operation, and the write timestamp in the unit of data. The processing device initiates the defect detection operation responsive to the BER condition not being expected for the calculated W2R (based on the write timestamp). The processing device can use an ERF condition and the write timestamp to determine whether to perform the defect detection operation. The processing device initiates the defect detection operation responsive to the ERF condition not being expected the calculated W2R (based on the write timestamp).
    Type: Application
    Filed: December 10, 2018
    Publication date: June 11, 2020
    Inventors: Zhengang Chen, Sai Krishna Mylavarapu, Zhenlei Shen, Tingjun Xie, Charles S. Kwong
  • Publication number: 20200177205
    Abstract: Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting layout constitutes a Latin Square (LS) layout.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 4, 2020
    Inventors: Wei Wu, Zhenlei Shen, Zhengang Chen
  • Patent number: 10559366
    Abstract: Apparatuses, systems, methods, and computer program products for dynamically determining boundary word line voltage shift are presented. An apparatus includes an array of non-volatile memory cells and a controller. A controller includes a trigger detection component that is configured to detect a trigger condition associated with a last programmed word line of a partially programmed erase block of an array of non-volatile memory cells. A controller includes a voltage component that is configured to determine a read voltage threshold for a last programmed word line of a partially programmed erase block in response to a trigger condition. A controller includes a voltage shift component that is configured to calculate, dynamically, a read voltage threshold shift for a last programmed word line based on a determined read voltage threshold for the last programmed word line and a baseline read voltage threshold.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 11, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zhenlei Shen, Pitamber Shukla, Philip Reusswig, Niles N. Yang, Anubhav Khandelwal
  • Patent number: 10452471
    Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to identify a most recently written portion of the set of non-volatile memory cells and to compare an error rate of data stored in the most recently written portion with a reference error rate from a reference portion of the set of non-volatile memory cells to determine whether the most recently written portion is fully written or partially written.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: October 22, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zhenlei Shen, Nian Niles Yang, Chao-Han Cheng
  • Publication number: 20190304550
    Abstract: Apparatuses, systems, methods, and computer program products for dynamically determining boundary word line voltage shift are presented. An apparatus includes an array of non-volatile memory cells and a controller. A controller includes a trigger detection component that is configured to detect a trigger condition associated with a last programmed word line of a partially programmed erase block of an array of non-volatile memory cells. A controller includes a voltage component that is configured to determine a read voltage threshold for a last programmed word line of a partially programmed erase block in response to a trigger condition. A controller includes a voltage shift component that is configured to calculate, dynamically, a read voltage threshold shift for a last programmed word line based on a determined read voltage threshold for the last programmed word line and a baseline read voltage threshold.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: Western Digital Technologies, Inc.
    Inventors: ZHENLEI SHEN, PITAMBER SHUKLA, PHILIP REUSSWIG, NILES N. YANG, ANUBHAV KHANDELWAL
  • Patent number: 10381097
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for performing read mode tuning. An apparatus includes an error rate storage circuit that determines error rate information. An apparatus includes a mode selection circuit that determines a read mode of a plurality of read modes for reading a set of memory cells based on error rate information. The plurality of read modes may include a fast read mode and a normal read mode. An apparatus includes a read circuit that performs a read on a set of memory cells based on a read mode.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 13, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Nian Niles Yang, Grishma Shah, Philip David Reusswig, Zhenlei Shen
  • Publication number: 20190130989
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for performing read mode tuning. An apparatus includes an error rate storage circuit that determines error rate information. An apparatus includes a mode selection circuit that determines a read mode of a plurality of read modes for reading a set of memory cells based on error rate information. The plurality of read modes may include a fast read mode and a normal read mode. An apparatus includes a read circuit that performs a read on a set of memory cells based on a read mode.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 2, 2019
    Applicant: Western Digital Technologies, Inc.
    Inventors: Nian Niles Yang, Grishma Shah, Philip David Reusswig, Zhenlei Shen
  • Publication number: 20190108090
    Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to identify a most recently written portion of the set of non-volatile memory cells and to compare an error rate of data stored in the most recently written portion with a reference error rate from a reference portion of the set of non-volatile memory cells to determine whether the most recently written portion is fully written or partially written.
    Type: Application
    Filed: October 11, 2017
    Publication date: April 11, 2019
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zhenlei Shen, Nian Niles Yang, Chao-Han Cheng
  • Patent number: 10108471
    Abstract: Systems and methods for controlling blocks in a memory device using a health indicator (such as the failed bit count) for the blocks are disclosed. However, the health indicator may exhibit noise, thereby resulting in an unreliable indicator of the health of the blocks in the memory device. In order to filter out the noise, a rolling average of the health indicator may be determined, and compared to the current health indicator. The comparison with the rolling average may indicate whether the current health indicator is an outlier, and thus should not be used. The health indicator may also be used to predict a future health indicator for different blocks in the memory device. Using the predicted future health indicator, the use of the blocks may be changed in order to more evenly wear the blocks.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: October 23, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Zhenlei Shen, Xinde Hu, Lei Chen, Yiwei Song