Abstract: A scaling factor for a data unit of a memory device is obtained. The scaling factor corresponds to a difference between a first error rate associated with a first set of memory access operations performed at the data unit and a second error rate associated with a second set of memory access operations performed at the data unit. A media management operation is scheduled on the data unit in view of the scaling factor.

Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.

Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.

Abstract: A system includes a memory device having groups of managed units and a processing device coupled to the memory device. The processing device, during power on of the memory device, causes a read operation to be performed at a subset of a group of managed units and determines a bit error rate related to data read from the subset of the group of managed units. The bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states. In response to the bit error rate satisfying a threshold criterion, the processing device causes a rewrite of the data stored at the group of managed units.

Abstract: Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting (EC) layout constitutes a first layout in the form of a Latin Square.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising receiving, from a host system, an enhanced erase command referencing a block; performing a lookup to determine whether the block is marked in a grown bad block (GBB) data structure used to track blocks that have a defective select gate; and responsive to determining that the block is marked in the GBB data structure, discarding the enhanced erase command.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a parameter value of a select gate associated with a first set of memory cells; responsive to determining that the parameter value satisfies a threshold criterion, marking the first block in a grown bad block (GBB) data structure; performing one or more pulse operations on the first block to invalidate data stored on the block; receiving, from a host system, an enhanced erase command referencing a second block; and responsive to determining that the second block is marked in the GBB data structure, discarding the enhanced erase command.

Abstract: It is determined whether a write disturb capability associated with a first location of a memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of memory units is remapped to a second location of the memory device, wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.

Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.

Abstract: A plurality of memory units residing in a first location of a memory device is identified, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device. It is determined whether a write disturb capability associated with the first location of the memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of logical addresses associated with the plurality of memory units is remapped to a second location of the memory device, wherein the second location of the memory device corresponds to a second layer of the plurality of layers of the memory device, and wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.

Abstract: A processing device of a memory sub-system is configured to determine, for a memory unit of the memory device, a plurality of write disturb counts associated with the memory unit, wherein each of the plurality of write disturb (WD) count is associated with a corresponding write disturb direction; compute, for the memory unit, a weighted WD count reflecting the plurality of write disturb counts; determine whether the weighted WD count meets a criterion; and responsive to determining that the weighted WD count meets the criterion, perform a refresh operation on the memory unit.

Abstract: A first error rate based on a first read operation performed on a memory device is obtained. An individual data unit of the memory device that satisfies a first threshold criterion associated with a defect candidate is determined. A defect verification operation on the individual data unit to obtain a second error rate is performed. The individual data unit that satisfies a second threshold criterion associated with a defect is determined.

Abstract: A request to read data at the memory device is received. A first read operation is performed to read the data at the memory device using a first read threshold voltage. The data read at the memory device using the first read threshold voltage is determined to be associated with a first unsuccessful correction of an error. Responsive to determining that the data read at the memory device using the first read threshold voltage is associated with the first unsuccessful correction of the error, a second read threshold voltage is stored at a register to replace a preread threshold voltage previously stored at the register that is associated with the memory device. The first preread threshold voltage was previously used to perform a preread operation at the memory device. A second read operation to read the data at the memory device is performed using the second read threshold voltage.

Abstract: A system comprises a plurality of memory devices storing a set of codewords and a processing device, operatively coupled to the plurality of memory devices, to perform operations including: detecting a power-on of the system; determining a read-retry trigger rate (TR) based on reading a subset of the codewords during a time interval directly after actual initialization of the plurality of memory devices, wherein the time interval includes a time period before entering a normal operating mode, and no full-memory refresh operation is performed during the normal operating mode; determining whether the TR satisfies a threshold criterion; and in response to the TR not satisfying the threshold criterion, initializing the full-memory refresh operation of the plurality of memory devices.

Abstract: A system includes a memory device having memory cells and a processing device operatively coupled to the memory device. The processing device is to perform operations including: determining a length of time the memory device has been powered off; and in response to determining that the length of time satisfies a threshold value: for each of multiple groups of memory cells, asserting a corresponding flag; determining, based on the length of time, one or more adjusted demarcation voltages to be used in reading a state of the multiple groups of memory cells; and storing the one or more adjusted demarcation voltages for use in performing memory operations.

Abstract: A command indicating a logical address and a length system is received from a host system. One or more memory units in a memory sub-system corresponding to the logical address and the length are identified. An indicator associated with the one or more memory units is set, to indicate that the one or more memory units are invalid. The one or more memory units are excluded from a media management operation performing in the memory sub-system.

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, identifying, by the processing device, a plurality of partitions located on a die of the memory device. The operations performed by the processing device further include selecting, based on evaluating a predefined criterion reflecting a physical layout of the die of the memory device, a first partition and a second partition of the plurality of partitions. The operations performed by the processing device further include generating a codeword comprising first data residing on the first partition and second data residing on the second partition.

Abstract: In response to a determination that an error rating condition associated with a memory device is satisfied, a first error correction operation is performed at the memory device to correct one or more first errors associated with a first memory access operation at the memory device. A detection is made that at least one of a state of the memory device has changed from a first state to a second state or a behavior of the memory device has changed from a first behavior level to a second behavior level. The error rating condition is modified in view of the at least one of the second state of the memory device or the second behavior level of the memory device. In response to a determination that the modified error rating condition is satisfied, a second error correction operation is performed at the memory device to correct one or more second errors associated with a second memory access operation performed at the memory device.

Abstract: A quality rating for a memory device to be installed at a memory sub-system is determined, where the quality rating corresponds to a performance of the memory device at one or more operating temperatures. A determination is made whether the quality rating for the memory device satisfies a first quality rating condition associated with a first temperature zone of two or more temperature zones of the memory sub-system. Responsive to the determination that the quality rating for the memory device satisfies the first quality rating condition, the memory device is assigned to be installed at a first memory device socket of the first temperature zone.

Abstract: A system includes a memory device having groups of managed units and a processing device coupled to the memory device. The processing device, during power on of the memory device, causes a read operation to be performed at a subset of a group of managed units and determines a bit error rate related to data read from the subset of the group of managed units. The bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states. In response to the bit error rate satisfying a threshold criterion, the processing device causes a rewrite of the data stored at the group of managed units.