Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command specifying a logical address; determining a physical address associated with the logical address; determining a portion of the memory device that is referenced by the physical address; determine an endurance factor associated with the portion; and increasing, by a value derived from the endurance factor, a media management metric associated with a management unit of the memory device, wherein the management unit is referenced by the physical address.

Abstract: A first error rate based on a first read operation performed on a memory device is obtained. An individual data unit of the memory device that satisfies a first threshold criterion associated with a defect candidate is determined. A defect verification operation on the individual data unit to obtain a second error rate is performed. The individual data unit that satisfies a second threshold criterion associated with a defect is determined.

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, identifying, by the processing device, a plurality of partitions located on a die of the memory device. The operations performed by the processing device further include selecting, based on evaluating a predefined criterion reflecting a physical layout of the die of the memory device, a first partition and a second partition of the plurality of partitions. The operations performed by the processing device further include generating a codeword comprising first data residing on the first partition and second data residing on the second partition.

Abstract: Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting (EC) layout constitutes a first layout in the form of a Latin Square.

Abstract: Respective life expectancies of a first data unit and a second data unit of the memory device is obtained. A first initial age value corresponding to the first data unit and a second initial age value corresponding to the second data unit are determined. A lower one of the first initial age value and the second initial age value is identified. A first media management operation on a corresponding one of the first data unit or the second data unit associated with the lower one of the first initial age value and the second initial age value is performed. A second media management operation on the first data unit and the second data unit is performed.

Abstract: A request to read data at the memory device is received. A first read operation is performed to read the data at the memory device using a first read threshold voltage. The data read at the memory device using the first read threshold voltage is determined to be associated with a first unsuccessful correction of an error. Responsive to determining that the data read at the memory device using the first read threshold voltage is associated with the first unsuccessful correction of the error, a second read threshold voltage is stored at a register to replace a preread threshold voltage previously stored at the register that is associated with the memory device. The first preread threshold voltage was previously used to perform a preread operation at the memory device. A second read operation to read the data at the memory device is performed using the second read threshold voltage.

Abstract: A scaling factor for a data unit of a memory device is obtained. The scaling factor corresponds to a difference between a first error rate associated with a first set of memory access operations performed at the data unit and a second error rate associated with a second set of memory access operations performed at the data unit. A media management operation is scheduled on the data unit in view of the scaling factor.

Abstract: A system comprises a plurality of memory devices storing a set of codewords and a processing device, operatively coupled to the plurality of memory devices, to perform operations including: detecting a power-on of the system; determining a read-retry trigger rate (TR) based on reading a subset of the codewords during a time interval directly after actual initialization of the plurality of memory devices, wherein the time interval includes a time period before entering a normal operating mode, and no full-memory refresh operation is performed during the normal operating mode; determining whether the TR satisfies a threshold criterion; and in response to the TR not satisfying the threshold criterion, initializing the full-memory refresh operation of the plurality of memory devices.

Abstract: An indication that an allocation unit of a memory sub-system has become unmapped can be received. In response to receiving the indication that the allocation unit of the memory sub-system has become unmapped, the allocation unit can be programmed with a data pattern. Data to be written to the unmapped allocation unit can be received. A write operation can be performed to program the received data at the unmapped allocation unit by using a read voltage that is based on the data pattern.

Abstract: A command pertaining to a non-volatile memory device on a memory sub-system is received from a host system. A portion of the non-volatile memory device has an association with the host system. In response to determining that the command is a dissociate instruction to dissociate the portion of the non-volatile memory device on the memory sub-system with the host system, remove the association of the portion of the non-volatile memory device on the memory sub-system with the host system.

Abstract: Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting layout constitutes a Latin Square (LS) layout.

Abstract: In response to a determination that an error rating condition associated with a memory device is satisfied, a first error correction operation is performed at the memory device to correct one or more first errors associated with a first memory access operation at the memory device. A detection is made that at least one of a state of the memory device has changed from a first state to a second state or a behavior of the memory device has changed from a first behavior level to a second behavior level. The error rating condition is modified in view of the at least one of the second state of the memory device or the second behavior level of the memory device. In response to a determination that the modified error rating condition is satisfied, a second error correction operation is performed at the memory device to correct one or more second errors associated with a second memory access operation performed at the memory device.

Abstract: A processing device of a memory sub-system performs an operation including obtaining, at a first time, a first scaling factor for a data unit of a set of data units of a memory device. The first scaling factor is associated with a first number of write operations performed at the data unit and a first number of read operations performed at the data unit. The processing device also performs an operation including calculating a first media management metric based on at least the first scaling factor, the first number of write operations, and the first number of read operations. In response to determining that the first media management metric satisfies a media management criterion, the processing device performs a media management operation on the data unit.

Abstract: A system includes a plurality of memory devices and a processing device (e.g., a controller), operatively coupled to the plurality of memory devices. The processing device is to detect a power-on of the system and determine a read-retry trigger rate (TR) of a subset of codewords of the plurality of memory devices during a time interval after an initialization of the memory component. The processing device is further to determine whether the TR satisfies a threshold criterion. In response to the TR not satisfying the threshold criterion, the processing device is to initialize a full-memory refresh of the plurality of memory devices.

Abstract: A first error rating for a first memory access operation performed for data stored at a memory device operating at a first state is determined. In response to a determination that the first error rating satisfies a first error rating condition associated with the first state of the memory device, a first error correction operation is performed at the memory device. A change of the state of the memory device from the first state to a second state is detected. A second error rating condition associated with the memory device is determined based on the second state of the memory device. A second error rating is determined for a second memory access operation performed at the memory device. In response to a determination that the second error rating satisfies the second error rating condition, a second error correction operation is performed at the memory device.

Abstract: A request to write data at a memory device is received. Responsive to receiving the request to write the data at the memory device, a first random value and a second random value is determined. Responsive to determining that the first random value does not satisfy a first threshold criterion and the second random value does not satisfy a second threshold criterion, a first write operation mode is selected from a plurality of write operations modes, and a write operation to write the data at the memory device is performed in accordance with the first write operation mode.

Abstract: A processing device in a memory sub-system receives an indication that a write back operation was performed for a management unit in a memory device. Responsive to receiving the indication that the write back operation was performed, the processing device initiates a read verify operation for the management unit and receives an indication of a number of write back errors associated with the management unit during the read verify operation. The processing device further determines whether the number of write back errors satisfies a read verify threshold criterion, and responsive to the number of write back errors satisfying the read verify threshold criterion, remaps the management unit to a different location on the memory device.

Abstract: A processing device of a memory sub-system performs an operation including obtaining, at a first time, a first scaling factor for a data unit of a set of data units of a memory device. The first scaling factor is associated with a first number of write operations performed at the data unit and a first number of read operations performed at the data unit. The processing device also performs an operation including calculating a first media management metric based on at least the first scaling factor, the first number of write operations, and the first number of read operations. In response to determining that the first media management metric satisfies a media management criterion, the processing device performs a media management operation on the data unit.

Abstract: A command pertaining to a non-volatile memory device on a memory sub-system is received from a host system. A portion of the non-volatile memory device has an association with the host system. In response to determining that the command is a dissociate instruction to dissociate the portion of the non-volatile memory device on the memory sub-system with the host system, remove the association of the portion of the non-volatile memory device on the memory sub-system with the host system.

Abstract: A first error rating for a first memory access operation performed for data stored at a memory device operating at a first state is determined. In response to a determination that the first error rating satisfies a first error rating condition associated with the first state of the memory device, a first error correction operation is performed at the memory device. A change of the state of the memory device from the first state to a second state is detected. A second error rating condition associated with the memory device is determined based on the second state of the memory device. A second error rating is determined for a second memory access operation performed at the memory device. In response to a determination that the second error rating satisfies the second error rating condition, a second error correction operation is performed at the memory device.