Abstract: A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.

Abstract: A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.

Abstract: Embodiments of the invention are directed to method of fabricating a semiconductor device. A non-limiting embodiment of the method includes performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate, wherein the fabrication operations include forming gate spacers along a gate region of the nanosheet FET device, wherein each of the gate spacers comprises an upper segment and a lower segment.

Abstract: Embodiments of the invention are directed to a computer-implemented method for generating a sleep optimization plan. A non-limiting example of the computer-implemented method includes receiving, by a processor, genetic data for a user. The method also includes receiving, by the processor, Internet of Things (IoT) device data for the user. The method also includes generating, by the processor, a sleep duration measurement for the user based at last in part upon the IoT device data. The method also includes generating, by the processor, a sleep optimization plan for the user based at least in part upon the genetic data.

Abstract: A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer over the source/drain, and forming an inter-level dielectric (ILD) layer over the sacrificial layer. The method further includes forming trenches that extend partially into the sacrificial layer, removing the sacrificial layer to expose an upper surface of the source/drain, and filling the trenches with at least one conducting material. The sacrificial layer is germanium (Ge) and the at least one conducting material includes three conducting materials.

Abstract: Embodiments of the invention are directed to a computer-implemented method for generating a sleep optimization plan. A non-limiting example of the computer-implemented method includes receiving, by a processor, genetic data for a user. The method also includes receiving, by the processor, Internet of Things (IoT) device data for the user. The method also includes generating, by the processor, a sleep duration measurement for the user based at last in part upon the IoT device data. The method also includes generating, by the processor, a sleep optimization plan for the user based at least in part upon the genetic data.

Abstract: A configuration of components formed on a semiconductor structure is provided. A non-limiting example of the configuration includes a substrate having a first section doped with a first dopant and a second section doped with a second dopant. The configuration further includes an insulator interposed between the first and second sections. A first fin extends upwardly from the first section, and second and third fins extend upwardly from the second section. A conductor is configured to be shared between proximal gates operably interposed between the first and second fins. A dielectric material is configured to separate proximal gates operably interposed between the second and third fins.

Abstract: A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer over the source/drain, and forming an inter-level dielectric (ILD) layer over the sacrificial layer. The method further includes forming trenches that extend partially into the sacrificial layer, removing the sacrificial layer to expose an upper surface of the source/drain, and filling the trenches with at least one conducting material. The sacrificial layer is germanium (Ge) and the at least one conducting material includes three conducting materials.

Abstract: A method is presented for reducing contact resistance and parasitic capacitance. The method includes forming a plurality of fins over a semiconductor substrate, forming a bottom source/drain region between the plurality of fins, forming a bottom spacer over the bottom source/drain region, forming high-k metal gates over the bottom spacers, and forming a top spacer over the high-k metal gates. The method further includes forming an interlayer dielectric (ILD) over the top spacer, recessing the ILD to expose top sections of the plurality of fins, depositing an epitaxial material over each of the top sections of the plurality of fins, forming a dielectric film over the epitaxial material such that air-gaps are created between the top sections of the plurality of fins and recessing the dielectric film to expose top sections of the epitaxial material and to deposit a silicide metal liner and a conductive material thereon.

Abstract: A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a pitch P. The first and second regions are separated by an isolation region with spacing S, wherein S is greater than P. A first insulating layer is deposited and recessed to a target depth in the first region, and to a second depth in the isolation region. The second depth is lower than the target depth. A first etch stop layer is formed over the recessed first insulating layer, and a second insulating layer is formed over the first etch stop layer to increase a level of insulating material in the isolation region to the same target depth in the first device region. The recessed first insulating layer, first etch stop layer, and second insulating layer form a uniform thickness shallow trench isolation layer.

Abstract: A semiconductor device that includes a first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region. The first plurality of fin structures includes adjacent fin structures separated by a lesser pitch than the adjacent fin structures in the second plurality of fin structures. At least one layer of dielectric material between adjacent fin structures, wherein a portion of the first plurality of fin structures extending above the at least one layer of dielectric material in the first device region is substantially equal to the portion of the second plurality of fin structures extending above the at least one layer of dielectric material in the second device region. Source and drain regions are present on opposing sides of a gate structure that is present on the fin structures.

Abstract: A configuration of components formed on a semiconductor structure is provided. A non-limiting example of the configuration includes a substrate having a first section doped with a first dopant and a second section doped with a second dopant. The configuration further includes an insulator interposed between the first and second sections. A first fin extends upwardly from the first section, and second and third fins extend upwardly from the second section. A conductor is configured to be shared between proximal gates operably interposed between the first and second fins. A dielectric material is configured to separate proximal gates operably interposed between the second and third fins.

Abstract: A method of forming vertical transport fin field effect transistors, including, forming a bottom source/drain layer on a substrate, forming a channel layer on the bottom source/drain layer, forming a recess in the channel layer on a second region of the substrate, wherein the bottom surface of the recess is below the surface of the channel layer on a first region, forming a top source/drain layer on the channel layer, where the top source/drain layer has a greater thickness on the second region of the substrate than on the first region of the substrate, and forming a vertical fin on the first region of the substrate, and a vertical fin on the second region of the substrate, wherein a first top source/drain is formed on the vertical fin on the first region, and a second top source/drain is formed on the vertical fin on the second region.

Abstract: A method for manufacturing a semiconductor device includes forming a first nanosheet device and forming a second nanosheet device spaced apart from the first nanosheet device in respective first and second regions corresponding to first and second types. The first and second nanosheet devices respectively include a first and a second plurality of work function metal layers, and a work function metal layer extends from the first and second plurality of work function metal layers in the space between the nanosheet devices. In the method, part of the work function metal layer is removed from the space between the nanosheet devices, and the removed part of the work function metal layer is replaced with a polymer brush layer. The first plurality of work function metal layers is selectively removed from the first region with respect to the polymer brush layer.

Abstract: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.

Abstract: A method of forming a long-channel fin field effect device is provided. The method includes forming a trench in a substrate, forming a pedestal in the trench, wherein the pedestal extends above the surface of the substrate, forming a sacrificial pillar on the pedestal, forming a rounded top surface on the sacrificial pillar to form a sacrificial support structure, forming a fin material layer on the exposed surface of the sacrificial support structure, and removing the sacrificial support structure to leave a free-standing inverted U-shaped fin.

Abstract: A semiconductor device having a uniform height across different fin densities includes a semiconductor substrate having fins etched therein and including dense fin regions and isolation regions without fins. One or more dielectric layers are formed at a base of the fins and the isolation regions and have a uniform height across the fins and the isolation regions. The uniform height includes a less than 2 nanometer difference across the one or more dielectric layers.

Abstract: A method of forming vertical transport fin field effect transistors, including, forming a bottom source/drain layer on a substrate, forming a channel layer on the bottom source/drain layer, forming a recess in the channel layer on a second region of the substrate, wherein the bottom surface of the recess is below the surface of the channel layer on a first region, forming a top source/drain layer on the channel layer, where the top source/drain layer has a greater thickness on the second region of the substrate than on the first region of the substrate, and forming a vertical fin on the first region of the substrate, and a vertical fin on the second region of the substrate, wherein a first top source/drain is formed on the vertical fin on the first region, and a second top source/drain is formed on the vertical fin on the second region.

Abstract: A semiconductor structure comprises a semiconductor substrate, an N-type stacked nanosheet channel structure formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures comprises a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer, and with the gate work function metal layer being separated from the channel regions by the gate dielectric layer. The gate dielectric and gate work function metal layers of the adjacent N-type and P-type stacked nanosheet channel structures are substantially eliminated from a shared gate region between the adjacent N-type and P-type stacked nanosheet channel structures.

Abstract: A configuration of components formed on a semiconductor structure is provided. A non-limiting example of the configuration includes a substrate having a first section doped with a first dopant and a second section doped with a second dopant. The configuration further includes an insulator interposed between the first and second sections. A first fin extends upwardly from the first section, and second and third fins extend upwardly from the second section. A conductor is configured to be shared between proximal gates operably interposed between the first and second fins. A dielectric material is configured to separate proximal gates operably interposed between the second and third fins.