Patents by Inventor Zhenxing Bi

Zhenxing Bi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FIELD EFFECT TRANSISTOR DEVICES WITH SELF-ALIGNED SOURCE/DRAIN CONTACTS AND GATE CONTACTS POSITIONED OVER ACTIVE TRANSISTORS
    Publication number: 20200144118
    Abstract: A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 7, 2020
    Inventors: Kangguo Cheng, Juntao Li, Zhenxing Bi, Dexin Kong
  • INTEGRATING EXTRA GATE VFET WITH SINGLE GATE VFET
    Publication number: 20200144124
    Abstract: Embodiments of the present invention are directed to techniques for integrating an extra gate (EG) vertical field effect transistor (VFET) with a single gate (SG) VFET. In a non-limiting embodiment of the invention, a bottom source or drain (S/D) layer is formed over a substrate. A first semiconductor fin is formed over the bottom S/D layer in a first region of the substrate and a second semiconductor fin is formed over the bottom S/D layer in a second region of the substrate. A block mask is formed over the first semiconductor fin and the second semiconductor fin is recessed. The second semiconductor fin is exposed to an isotropic or anisotropic fin trim.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 7, 2020
    Inventors: ZHENXING BI, Kangguo Cheng, JUNLI WANG, PENG XU
  • INTEGRATION SCHEME FOR NON-VOLATILE MEMORY ON GATE-ALL-AROUND STRUCTURE
    Publication number: 20200135937
    Abstract: A integrated device including a non-volatile memory (NVM) and a nanosheet field effect transistor (FET) and a method of fabricating the device include patterning fins for a channel region of the NVM and the FET. The method also includes depositing an organic planarization layer (OPL) and a block mask to protect the fins for the channel region of the FET, conformally depositing a set of layers that make up an NVM structure in conjunction with the channel region of the NVM while protecting the fins for the channel region of the FET with the OPL and the block mask, and removing the OPL and the block mask protecting the fins for the channel region of the FET. Source and drain regions of the NVM and the FET are formed, and a gate of the FET is formed while protecting the NVM by depositing another OPL and another block mask.
    Type: Application
    Filed: October 24, 2018
    Publication date: April 30, 2020
    Inventors: Dexin Kong, Zhenxing Bi, Zheng Xu, Kangguo Cheng
  • NANOSHEET FET BOTTOM ISOLATION
    Publication number: 20200135852
    Abstract: A technique relates to a semiconductor device. A rare earth material is formed on a substrate. An isolation layer is formed at an interface of the rare earth material and the substrate. Channel layers are formed over the isolation layer. Source or drain (S/D) regions are formed on the isolation layer.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Inventors: RUQIANG BAO, ZHENXING BI, KANGGUO CHENG, ZHENG XU
  • INTEGRATION SCHEME FOR NON-VOLATILE MEMORY ON GATE-ALL-AROUND STRUCTURE
    Publication number: 20200135938
    Abstract: A integrated device including a non-volatile memory (NVM) and a nanosheet field effect transistor (FET) and a method of fabricating the device include patterning fins for a channel region of the NVM and the FET. The method also includes depositing an organic planarization layer (OPL) and a block mask to protect the fins for the channel region of the FET, conformally depositing a set of layers that make up an NVM structure in conjunction with the channel region of the NVM while protecting the fins for the channel region of the FET with the OPL and the block mask, and removing the OPL and the block mask protecting the fins for the channel region of the FET. Source and drain regions of the NVM and the FET are formed, and a gate of the FET is formed while protecting the NVM by depositing another OPL and another block mask.
    Type: Application
    Filed: November 6, 2019
    Publication date: April 30, 2020
    Inventors: Dexin Kong, Zhenxing Bi, Zheng Xu, Kangguo Cheng
  • TRANSISTOR WITH IMPROVED SELF-ALIGNED CONTACT
    Publication number: 20200135561
    Abstract: Systems, methods, and devices facilitating a transistor with an improved self-aligned contact are provided. In one example, a method comprises depositing a dielectric layer onto a first gate region and a second gate region of a semiconductor device, wherein the first gate region and the second gate region are separated by a substrate contact region, and wherein the dielectric layer has a first etch sensitivity to an inter-layer dielectric; and depositing a sacrificial layer onto the dielectric layer, wherein the sacrificial layer has a second etch sensitivity to the inter-layer dielectric that is greater than the first etch sensitivity.
    Type: Application
    Filed: October 29, 2018
    Publication date: April 30, 2020
    Inventors: Kangguo Cheng, Zhenxing Bi, Juntao Li, Dexin Kong
  • AREA SELECTIVE CYCLIC DEPOSITION FOR VFET TOP SPACER
    Publication number: 20200135893
    Abstract: Embodiments of the present invention are directed to techniques for forming a vertical field effect transistor (VFET) top spacer using an area selective cyclic deposition. In a non-limiting embodiment of the invention, a first semiconductor fin is formed over a substrate. A second semiconductor fin is formed over the substrate and adjacent to the first semiconductor fin. A dielectric isolation region is formed between the first semiconductor fin and the second semiconductor fin. A top spacer is formed between the first semiconductor fin and the second semiconductor fin by cyclically depositing dielectric layers over the dielectric isolation region. The dielectric layers are inhibited from depositing on a surface of the first semiconductor fin and on a surface of the second semiconductor fin during the cyclic deposition process.
    Type: Application
    Filed: October 24, 2018
    Publication date: April 30, 2020
    Inventors: ZHENXING BI, Kangguo Cheng, YONGAN Xu, Yi Song
  • NANOSHEET FET BOTTOM ISOLATION
    Publication number: 20200135853
    Abstract: A technique relates to a semiconductor device. A rare earth material is formed on a substrate. An isolation layer is formed at an interface of the rare earth material and the substrate. Channel layers are formed over the isolation layer. Source or drain (S/D) regions are formed on the isolation layer.
    Type: Application
    Filed: November 19, 2019
    Publication date: April 30, 2020
    Inventors: RUQIANG BAO, ZHENXING BI, Kangguo Cheng, ZHENG XU
  • Highly Selective Dry Etch Process for Vertical FET STI Recess
    Publication number: 20200126805
    Abstract: Highly selective dry etching techniques for VFET STI recess are provided. In one aspect, a method for dry etching includes: contacting a wafer including an oxide with at least one etch gas under conditions sufficient to etch the oxide at a rate of less than about 30 ?/min; removing a byproduct of the etch from the wafer using a thermal treatment; and repeating the contacting step followed by the removing step multiple times until a desired recess of the oxide has been achieved. A method of forming a VFET device is also provided.
    Type: Application
    Filed: October 19, 2018
    Publication date: April 23, 2020
    Inventors: Zhenxing Bi, Muthumanickam Sankarapandian, Richard A. Conti, Michael P. Belyansky
  • Low undercut N-P work function metal patterning in nanosheet replacement metal gate process
    Patent number: 10629495
    Abstract: A semiconductor structure comprises a semiconductor substrate, an N-type stacked nanosheet channel structure formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures comprises a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer, and with the gate work function metal layer being separated from the channel regions by the gate dielectric layer. The gate dielectric and gate work function metal layers of the adjacent N-type and P-type stacked nanosheet channel structures are substantially eliminated from a shared gate region between the adjacent N-type and P-type stacked nanosheet channel structures.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Indira Seshadri, Ekmini Anuja De Silva, Jing Guo, Romain J. Lallement, Ruqiang Bao, Zhenxing Bi, Sivananda Kanakasabapathy
  • Resistor fins
    Patent number: 10629589
    Abstract: A technique relates to forming resistor fins on a substrate. A shallow trench isolation material is formed on dummy fins and the substrate, and the dummy fins are formed on the substrate. Predefined ones of the dummy fins are removed, thereby forming voids in the shallow trench isolation material corresponding to previous locations of the predefined ones of the dummy fins. A first material is deposited into the voids. The height of the first material is reduced, thereby forming trenches in the shallow trench isolation material. A second material is deposited into the trenches to be on top of the first material, thereby forming the resistor fins of a resistor device. A metal contact layer is formed so as to contact a top surface of the first material at predefined locations.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Approach to bottom dielectric isolation for vertical transport fin field effect transistors
    Patent number: 10629702
    Abstract: A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Thamarai S. Devarajan, Balasubramanian Pranatharthiharan, Sanjay C. Mehta, Muthumanickam Sankarapandian
  • STACKED NANOSHEET COMPLEMENTARY METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR DEVICES
    Publication number: 20200119015
    Abstract: A method of forming a stacked nanosheet complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) device is provided. The method includes forming a plurality of semiconductor layers on a substrate, and patterning the plurality of semiconductor layers to form a plurality of multi-layer nanosheet fins with a fill layer between the multi-layer nanosheet fins and an endwall support on opposite ends of the nanosheet fins. The method further includes reducing the height of the fill layer to expose at least a top three semiconductor nanosheet segments of the multi-layer nanosheet fins, and removing two of the at least top three semiconductor nanosheet segments. The method further includes forming a protective layer on one of the at least top three semiconductor nanosheet segments.
    Type: Application
    Filed: October 12, 2018
    Publication date: April 16, 2020
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li
  • VERTICALLY STACKED NANOSHEET CMOS TRANSISTOR
    Publication number: 20200118892
    Abstract: Embodiments of the present invention are directed to techniques for generating vertically stacked nanosheet CMOS (Complementary Metal Oxide Semiconductor) transistor architectures. In a non-limiting embodiment of the invention, a first rare earth oxide layer is formed over a substrate. An n-FET nanosheet stack is formed on the rare earth oxide layer. The n-FET nanosheet stack includes a first nanosheet. A second rare earth oxide layer is formed on the n-FET nanosheet stack. A p-FET nanosheet stack is formed on the second rare earth oxide layer. The p-FET nanosheet stack includes a second nanosheet.
    Type: Application
    Filed: November 22, 2019
    Publication date: April 16, 2020
    Inventors: Kangguo Cheng, JUNTAO LI, ZHENXING BI
  • SELF-ALIGNED FIN RECESSES IN NANOSHEET FIELD EFFECT TRANSISTORS
    Publication number: 20200118881
    Abstract: Semiconductor devices and methods of forming the same include etching a stack of alternating channel and sacrificial layers to form a fin. The etch depth is controlled by a signal layer embedded in a substrate under the stack. Source and drain regions are formed on ends of the channel layers. The sacrificial layers are etched away and a gate stack is formed over and between the channel layers.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 16, 2020
    Inventors: Zhenxing Bi, Kangguo Cheng, Wenyu Xu, Xin Miao
  • VERTICALLY STACKED NANOSHEET CMOS TRANSISTOR
    Publication number: 20200118891
    Abstract: Embodiments of the present invention are directed to techniques for generating vertically stacked nanosheet CMOS (Complementary Metal Oxide Semiconductor) transistor architectures. In a non-limiting embodiment of the invention, a first rare earth oxide layer is formed over a substrate. An n-FET nanosheet stack is formed on the rare earth oxide layer. The n-FET nanosheet stack includes a first nanosheet. A second rare earth oxide layer is formed on the n-FET nanosheet stack. A p-FET nanosheet stack is formed on the second rare earth oxide layer. The p-FET nanosheet stack includes a second nanosheet.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 16, 2020
    Inventors: Kangguo Cheng, JUNTAO LI, ZHENXING BI
  • TRANSISTOR WITH REDUCED GATE RESISTANCE AND IMPROVED PROCESS MARGIN OF FORMING SELF-ALIGNED CONTACT
    Publication number: 20200111706
    Abstract: A semiconductor structure is provided that includes a gate conductor structure having a middle portion that has a vertical thickness that is greater than a vertical thickness of each end portion, and a self-aligned dielectric gate cap located on the gate conductor structure and having a middle portion that has a vertical thickness that is less than a vertical thickness of each end portion. The aforementioned gate conductor structure, which is taller in the middle and shorter at the edges, has reduced gate resistance, while the aforementioned self-aligned dielectric gate cap, which is taller at the edges and shorter in the middle, increases process margin for contact formation.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventors: Kangguo Cheng, Zhenxing Bi, Juntao Li, Dexin Kong
  • Integration scheme for non-volatile memory on gate-all-around structure
    Patent number: 10615288
    Abstract: A integrated device including a non-volatile memory (NVM) and a nanosheet field effect transistor (FET) and a method of fabricating the device include patterning fins for a channel region of the NVM and the FET. The method also includes depositing an organic planarization layer (OPL) and a block mask to protect the fins for the channel region of the FET, conformally depositing a set of layers that make up an NVM structure in conjunction with the channel region of the NVM while protecting the fins for the channel region of the FET with the OPL and the block mask, and removing the OPL and the block mask protecting the fins for the channel region of the FET. Source and drain regions of the NVM and the FET are formed, and a gate of the FET is formed while protecting the NVM by depositing another OPL and another block mask.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dexin Kong, Zhenxing Bi, Zheng Xu, Kangguo Cheng
  • VERTICAL SILICON/SILICON-GERMANIUM TRANSISTORS WITH MULTIPLE THRESHOLD VOLTAGES
    Publication number: 20200105614
    Abstract: A method of forming vertical fin field effect transistors, including, forming a silicon-germanium cap layer on a substrate, forming at least four vertical fins and silicon-germanium caps from the silicon-germanium cap layer and the substrate, where at least two of the at least four vertical fins is in a first subset and at least two of the at least four vertical fins is in a second subset, forming a silicon-germanium doping layer on the plurality of vertical fins and silicon-germanium caps, removing the silicon-germanium doping layer from the at least two of the at least four vertical fins in the second subset, and removing the silicon-germanium cap from at least one of the at least two vertical fins in the first subset, and at least one of the at least two vertical fins in the second subset.
    Type: Application
    Filed: November 18, 2019
    Publication date: April 2, 2020
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • FinFET transistor gate and epitaxy formation
    Patent number: 10608121
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures that reduce shallow trench isolation (STI) undercutting, floating gates, and gate voids without degrading epitaxy quality. The method includes forming a first and second semiconductor fin on a substrate. A buffer layer is formed on a surface of the substrate between the first and second semiconductor fins and a semiconducting layer is formed on the buffer layer. The buffer layer is selectively removed and replaced with a dielectric layer. A first gate is formed over a first channel region of the first semiconductor fin and a second gate is formed over a second channel region of the first semiconductor fin. Source and drain epitaxy regions are selectively formed on surfaces of the first gate.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 31, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Zhenxing Bi, Kangguo Cheng, Zheng Xu