Patents by Inventor Zhenyu Lu

Zhenyu Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10892274
    Abstract: Embodiments of 3D memory devices and fabricating methods are disclosed. The method can comprise: forming an alternating dielectric stack on a substrate; forming a channel hole penetrating the alternating dielectric stack to expose a surface of the substrate; forming an epitaxial layer on a bottom of the channel hole; forming a functional layer covering a sidewall of the channel hole and a top surface of the epitaxial layer; forming a protecting layer covering the functional layer; removing portions of the functional layer and the protecting layer to form an opening to expose a surface of the epitaxial layer; expanding the opening laterally to increase an exposed area of the epitaxial layer at the bottom of the channel hole; and forming a channel structure on the sidewall of the channel hole and being in electrical contact with the epitaxial layer through the expanded opening.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: January 12, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yushi Hu, Qian Tao, Haohao Yang, Jin Wen Dong, Jun Chen, Zhenyu Lu
  • Publication number: 20210005625
    Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 7, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiaowang DAI, Zhenyu LU, Jun CHEN, Qian TAO, Yushi HU, Jifeng ZHU, Jin Wen DONG, Ji XIA, Zhong ZHANG, Yan Ni LI
  • Publication number: 20210005621
    Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yushi HU, Zhenyu LU, Qian TAO, Jun CHEN, Simon Shi-Ning YANG, Steve Weiyi YANG
  • Patent number: 10886291
    Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: January 5, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Feng Pan, Xianjin Wan, Baoyou Chen
  • Publication number: 20200411547
    Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 31, 2020
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu LU, Yu Ru HUANG, Qian TAO, Yushi HU, Jun CHEN, Xiaowang DAI, Jifeng ZHU, Yongna LI, Lidong SONG
  • Patent number: 10879259
    Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatma Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan
  • Publication number: 20200402986
    Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, a doped ferroelectric layer disposed between the first electrode and the second electrode. The doped ferroelectric layer includes oxygen and one or more ferroelectric metals. The doped ferroelectric layer further includes a plurality of dopants including at least one dopant from one of Group II elements, Group III elements, or Lanthanide elements. The plurality of dopants are different from the one or more ferroelectric metals.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Inventor: Zhenyu Lu
  • Patent number: 10868031
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate and a multiple-stack staircase structure. The multiple-stack staircase structure can include a plurality of staircase structures stacked over the substrate. Each one of the plurality of staircase structures can include a plurality of conductor layers each between two insulating layers. The memory device can also include a filling structure over the multiple-stack staircase structure, a semiconductor channel extending through the multiple-stack staircase structure, and a supporting pillar extending through the multiple-stack staircase structure and the filling structure. The semiconductor channel can include unaligned sidewall surfaces, and the supporting pillar can include aligned sidewall surfaces.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: December 15, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jun Liu, Zongliang Huo, Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Sizhe Li, Zhao Hui Tang, Yu Ting Zhou, Zhaosong Li
  • Patent number: 10867678
    Abstract: Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a memory stack disposed above the peripheral device and including a plurality of conductor/dielectric layer pairs, and a plurality of memory strings. Each of the memory strings extends vertically through the memory stack and includes a drain select gate and a source select gate above the drain select gate. Edges of the conductor/dielectric layer pairs in a staircase structure of the memory stack along a vertical direction away from the substrate are staggered laterally toward the memory strings.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 15, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jun Chen, Jifeng Zhu, Zhenyu Lu, Yushi Hu, Jin Wen Dong, Lan Yao
  • Patent number: 10861862
    Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, a doped ferroelectric layer disposed between the first electrode and the second electrode. The doped ferroelectric layer includes oxygen and one or more ferroelectric metals. The doped ferroelectric layer further includes a plurality of dopants including at least one dopant from one of Group II elements, Group III elements, or Lanthanide elements. The plurality of dopants are different from the one or more ferroelectric metals.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: December 8, 2020
    Assignee: WUXI PETABYTE TECHNOLOGIES CO, LTD.
    Inventor: Zhenyu Lu
  • Patent number: 10861000
    Abstract: Method and device for processing a payment are disclosed. The method is performed at a user device and includes: receiving a user instruction for starting a payment through a pre-set payment platform; selecting a respective loading process from a plurality of loading processes for invoking a payment application, wherein: the plurality of loading processes include: a first loading process for invoking the payment application immediately in a foreground process and a second loading process for simulating at least one payment interface of the payment application in the purchase application before loading the payment application in the user device; and presenting a first payment interface at the mobile terminal in response to the user instruction and the selection of the respective loading process.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: December 8, 2020
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Wei Mao, Yuewei Chen, Xing Liang, Bin Zhang, Qiang Lu, Deyuan Li, Zhonghua Lai, Zhenyu Xu
  • Patent number: 10860666
    Abstract: A computing device hosting a website of a business may be operable to receive a first search input comprising a term submitted via a search bar on the website. Upon performing an internal search for the term with no result, the computing device may output information on the no-result. The computing device may then perform, using one or more external search engines, a search for the term. Search results of the search, performed using the external search engine(s), may be analyzed. Based on a result of the analysis, one or more particular character strings related to the term may be identified. The computing device may generate and store, based on the identifying of the particular character string(s), one or more alternative search suggestions. Upon subsequently receiving an input comprising at least a portion of the term entered in the search bar, the computing device may output the alternative search suggestion(s).
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: December 8, 2020
    Assignee: TRANSFORM SR BRANDS LLC
    Inventors: Rongkai Zhao, Zhenyu Lu, Kenneth Katschke
  • Publication number: 20200381360
    Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng ZHU, Jun CHEN, Si Ping HU, Zhenyu LU
  • Patent number: 10847532
    Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: November 24, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Feng Pan, Xianjin Wan, Baoyou Chen
  • Patent number: 10847528
    Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: November 24, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiaowang Dai, Zhenyu Lu, Jun Chen, Qian Tao, Yushi Hu, Jifeng Zhu, Jin Wen Dong, Ji Xia, Zhong Zhang, Yan Ni Li
  • Patent number: 10847531
    Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: November 24, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Lidong Song, Yongna Li, Feng Pan, Steve Weiyi Yang, Wenguang Shi
  • Publication number: 20200364748
    Abstract: In an implementation, guiding a service flow is described. Historical behavior data of one or more users who use a target service is obtained for the target service. The historical behavior data is analyzed to obtain one or more user features. One or more target users are selected from one or more users who do not use the target service based on the one or more user features. Each target user has at least one of the one or more user features. Service flow guiding information is sent to each target user. The service flow guiding information guides each target user to use the target service.
    Type: Application
    Filed: July 31, 2020
    Publication date: November 19, 2020
    Applicant: Alibaba Group Holding Limited
    Inventors: Weiwei Ding, Chen Tao, Feng Jin, Zhenyu Lu, Jiajun Wen, Yonggang Du, Wenming He, Zhaolin Feng, Zhirong Yang, Kai Yang
  • Patent number: 10833099
    Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Zhenyu Lu, Roger W. Lindsay, Akira Goda, John Hopkins
  • Patent number: 10804287
    Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 13, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Yu Ru Huang, Qian Tao, Yushi Hu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Yongna Li, Lidong Song
  • Patent number: 10804279
    Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: October 13, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yushi Hu, Zhenyu Lu, Qian Tao, Jun Chen, Simon Shi-Ning Yang, Steve Weiyi Yang