Patents by Inventor Zhenyu Lu

Zhenyu Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11462474
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, a plurality of NAND strings on the substrate, one or more peripheral devices above the NAND strings, a single crystalline silicon layer above the peripheral devices, and one or more interconnect layers between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: October 4, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
  • Publication number: 20220238556
    Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.
    Type: Application
    Filed: April 19, 2022
    Publication date: July 28, 2022
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Jun Chen, LongDong Liu, Meng Wang
  • Patent number: 11380701
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: July 5, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yue Qiang Pu, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
  • Publication number: 20220208677
    Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.
    Type: Application
    Filed: March 14, 2022
    Publication date: June 30, 2022
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng ZHU, Jun CHEN, Si Ping HU, Zhenyu LU
  • Publication number: 20220181483
    Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.
    Type: Application
    Filed: February 23, 2022
    Publication date: June 9, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Zhenyu Lu, Hongbin Zhu, Gordon A. Haller, Roger W. Lindsay, Andrew Bicksler, Brian J. Cleereman, Minsoo Lee
  • Patent number: 11309327
    Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 19, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Jun Chen, LongDong Liu, Meng Wang
  • Patent number: 11289611
    Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Zhenyu Lu, Hongbin Zhu, Gordon A. Haller, Roger W. Lindsay, Andrew Bicksler, Brian J. Cleereman, Minsoo Lee
  • Patent number: 11276642
    Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: March 15, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Jun Chen, Si Ping Hu, Zhenyu Lu
  • Patent number: 11271004
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: March 8, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yue Qiang Pu, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
  • Patent number: 11264397
    Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: March 1, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yushi Hu, Zhenyu Lu, Qian Tao, Jun Chen, Simon Shi-Ning Yang, Steve Weiyi Yang
  • Patent number: 11211397
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 28, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Jun Chen, Jifeng Zhu, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
  • Patent number: 11211393
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: December 28, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yue Qiang Pu, Jin Wen Dong, Jun Chen, Zhenyu Lu, Qian Tao, Yushi Hu, Zhao Hui Tang, Li Hong Xiao, Yu Ting Zhou, Sizhe Li, Zhaosong Li
  • Publication number: 20210399001
    Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.
    Type: Application
    Filed: September 2, 2021
    Publication date: December 23, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiaowang DAI, Zhenyu LU, Jun CHEN, Qian TAO, Yushi HU, Jifeng ZHU, Jin Wen DONG, Ji XIA, Zhong ZHANG, Yan Ni LI
  • Publication number: 20210366931
    Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Inventors: Hongbin Zhu, Zhenyu Lu, Gordon Haller, Jie Sun, Randy J. Koval, John Hopkins
  • Patent number: 11145666
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: October 12, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
  • Patent number: 11133325
    Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: September 28, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiaowang Dai, Zhenyu Lu, Jun Chen, Qian Tao, Yushi Hu, Jifeng Zhu, Jin Wen Dong, Ji Xia, Zhong Zhang, Yan Ni Li
  • Publication number: 20210296341
    Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng ZHU, Zhenyu Lu, Jun Chen, Yushi Hu, Qian Tao, Simon Shi-Ning Yang, Steve Weiyi Yang
  • Patent number: 11101276
    Abstract: Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: August 24, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Si Ping Hu, Xiaowang Dai, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
  • Patent number: 11088168
    Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Zhenyu Lu, Gordon Haller, Jie Sun, Randy J. Koval, John Hopkins
  • Patent number: 11062353
    Abstract: In an implementation, guiding a service flow is described. Historical behavior data of one or more users who use a target service is obtained for the target service. The historical behavior data is analyzed to obtain one or more user features. One or more target users are selected from one or more users who do not use the target service based on the one or more user features. Each target user has at least one of the one or more user features. Service flow guiding information is sent to each target user. The service flow guiding information guides each target user to use the target service.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: July 13, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventors: Weiwei Ding, Chen Tao, Feng Jin, Zhenyu Lu, Jiajun Wen, Yonggang Du, Wenming He, Zhaolin Feng, Zhirong Yang, Kai Yang