Abstract: A computing device hosting a website of a business may be operable to receive a first search input comprising a term submitted via a search bar on the website. Upon performing an internal search for the term with no result, the computing device may output information on the no-result. The computing device may then perform, using one or more external search engines, a search for the term. Search results of the search, performed using the external search engine(s), may be analyzed. Based on a result of the analysis, one or more particular character strings related to the term may be identified. The computing device may generate and store, based on the identifying of the particular character string(s), one or more alternative search suggestions. Upon subsequently receiving an input comprising at least a portion of the term entered in the search bar, the computing device may output the alternative search suggestion(s).

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A computing device hosting a website of a business may be operable to receive a first search input comprising a term submitted via a search bar on the website. Upon performing an internal search for the term with no result, the computing device may output information on the no-result. The computing device may then perform, using one or more external search engines, a search for the term. Search results of the search, performed using the external search engine(s), may be analyzed. Based on a result of the analysis, one or more particular character strings related to the term may be identified. The computing device may generate and store, based on the identifying of the particular character string(s), one or more alternative search suggestions. Upon subsequently receiving an input comprising at least a portion of the term entered in the search bar, the computing device may output the alternative search suggestion(s).

Abstract: A method for forming a memory device is provided. An alternating dielectric stack is formed on a substrate. The alternating dielectric stack includes a dielectric layer pair, and the dielectric layer pair includes a first dielectric layer and a second dielectric layer different from the first dielectric layer. A barrier structure extending vertically through the alternating dielectric stack and laterally separating the alternating dielectric stack into a first portion and a second portion is formed. The barrier structure has an unclosed shape. The first dielectric layer in the second portion of the alternating dielectric stack is replaced with a conductor layer to form an alternating conductor/dielectric stack including the conductor layer and a third dielectric layer. A through array contact structure extending vertically through the first portion of the alternating dielectric stack to the substrate is formed.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.

Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a method of forming a ferroelectric memory cell is disclosed. A first electrode is formed. A doped ferroelectric layer is formed in contact with the first electrode. The doped ferroelectric layer includes oxygen and one or more ferroelectric metals. The doped ferroelectric layer further includes a plurality of dopants including at least one dopant from one of Group II elements, Group III elements, or Lanthanide elements. The plurality of dopants are different from the one or more ferroelectric metals. A second electrode is formed in contact with the doped ferroelectric layer.

Abstract: A three-dimensional (3D) memory device includes a staircase region including a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, and a through array contact extending vertically through the first stack. The first stack includes first and second dielectric layers arranged alternately in a vertical direction. The second stack includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure includes an unclosed shape.

Abstract: A memory device includes a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, a through array contact structure extending vertically through the first stack, and a slit structure extending through the second stack along a first lateral direction perpendicular to a vertical direction and including a conductive structure. The first stack includes first dielectric layers and second dielectric layers arranged alternately in the vertical direction. The second stack includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure includes two parallel first sub-barrier structures.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A three-dimensional (3D) NAND memory device includes a substrate, a staircase region including a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, and a through array contact extending vertically through the first stack to the substrate. The first stack is disposed on the substrate and includes first and second dielectric layers arranged alternately in a vertical direction. The second stack is disposed on the substrate and includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure has an unclosed shape.

Abstract: A memory device includes an alternating layer stack including conductive/dielectric layer pairs stacked in a first direction, a first insulating layer on the alternating layer stack, a thickness of the first insulating layer being larger than a thickness of the dielectric layer, and a channel structure extending through the alternating layer stack and the first insulating layer along the first direction. The channel structure includes an epitaxial layer disposed at a first end of the channel structure away from the first insulating layer, a functional layer on the epitaxial layer and extending along the first direction, a channel layer covering a sidewall of the functional layer and in contact with the epitaxial layer, and a filling structure covering a sidewall of the channel layer.

Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.

Abstract: A memory device includes a plurality of memory cells and a routing interconnection structure in electric contact with the memory cells. Each memory cell includes at least one first transistor, a cell interconnection structure formed over the transistor and in electrical contact with the transistor, the cell interconnection structure including a cell plate disposed at a top layer of the cell interconnection structure, and at least one capacitor electrically coupled to the first transistor through the cell interconnection structure. Each capacitor includes a first electrode, a second electrode, and a ferroelectric layer disposed between the first electrode and the second electrode. The routing interconnection structure includes a first conductive layer, and a first via structure disposed on the first conductive layer. The first via structure is in electrical contact with the first electrode through a second conductive layer. The first conductive layer is beneath the second conductive layer.

Abstract: A memory device includes a plurality of memory cells and a periphery circuit. Each memory cell includes at least one first transistor, at least one first interconnection layer formed over the first transistor and in electrical contact with the at least one transistor, and at least one capacitor electrically coupled to the at least one first transistor through the at least one first interconnection layer. A routing structure disposed over the plurality of memory cells and the periphery circuit to electrically connect the plurality of memory cells and the periphery circuit. A second interconnection layer is disposed over the routing structure. The at least one capacitor is disposed between the routing structure and a topmost conductive layer of the at least one first interconnection layer. The second interconnection layer includes no more than one conductive layer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A semiconductor device includes a first stacked layer, an insulating layer disposed over the first stacked layer, a second stacked layer disposed over the insulating layer, a channel structure extending through the second stacked layer, the insulating layer and the first stacked layer, a first filling structure, and a second filling structure. The channel structure includes a first channel structure extending through the first stacked layer, a second channel structure extending through the second stacked layer, and a third channel structure disposed in the insulating layer and in contact with the first and second channel structures. A size of the third channel structure in a first direction is larger than a size of the first channel structure in the first direction. The first direction is perpendicular to a stacking direction of the first stacked layer. The first filling structure is in contact with an inner surface of the first channel structure.

Abstract: In an example, a memory device includes a first stack structure and a second stack structure over the first stack structure. Each of the first stack structure and the second stack structure includes alternately stacked conductor layers and first insulating layers. The memory device also includes a first channel structure extending through the first stack structure, and a second channel structure extending through the second stack structure and connected with the first channel structure. A width of an end of the first channel structure closer to the second channel structure is greater than that of the second channel structure closer to the first channel structure. The memory device further includes a pillar structure extending through the first stack structure and the second stack structure. The pillar structure includes a metal layer.

Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.