Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

Abstract: A semiconductor device includes a first device fin and a second device fin that are each located in a first region of the semiconductor device. The first region has a first pattern density. A first dummy fin is located in the first region. The first dummy fin is disposed between the first device fin and the second device fin. The first dummy fin has a first height. A third device fin and a fourth device fin are each located in a second region of the semiconductor device. The second region has a second pattern density that is greater the first pattern density. A second dummy fin is located in the second region. The second dummy fin is disposed between the third device fin and the fourth device fin. The second dummy fin has a second height that is greater than the first height.

Abstract: Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.

Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures stacked in a vertical direction over a substrate, and a first dummy fin structure between the first nanostructures and the second nanostructures. The semiconductor device structure includes a first gate structure formed over the first nanostructures, wherein the first gate structure includes a gate dielectric layer, and the gate dielectric layer is in direct contact with a sidewall surface of the first dummy fin structure.

Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

Abstract: The control module outputs a control signal to control the first image capture module and the second image capture module to be in a working state in a time-sharing manner. A first signal interface is electrically connected to the first node. The first optimization unit is electrically connected between the first node and the first image capture module, and the second optimization unit is electrically connected between the first node and the second image capture module. The first optimization unit is configured to ensure the smoothness of a curve of a first image signal corresponding to a first image captured when the first image capture module is in the working state, and the second optimization unit is configured to ensure the smoothness of a curve of a second image signal corresponding to a second image captured when the second image capture module is in the working state.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.

Abstract: A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure also includes a first bottom layer formed adjacent to the first nanostructures, and a first dielectric layer formed over the first bottom layer. The semiconductor device structure further includes a first source/drain (S/D) structure formed over the first dielectric layer, and the first S/D structure is isolated from the first bottom layer by the first dielectric layer.

Abstract: A semiconductor device includes a first fin, a second fin, a first gate electrode having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate electrode having a portion that at least partially wraps around the upper portion of the first fin, and a gate-cut feature having a first portion in the first gate electrode between the first and second portions of the first gate electrode. The gate-cut feature is at least partially filled with one or more dielectric materials. In a direction of a longitudinal axis of the first fin, the gate-cut feature has a second portion extending to a sidewall of the second gate electrode.

Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first bottom layer formed adjacent to the first nanostructures, and a first insulating layer formed over the first bottom layer. The semiconductor device structure includes a first source/drain (S/D) structure formed over the first insulating layer, and the first insulating layer is in direct contact with one of the first nanostructures.

Abstract: An approach is provided in which the approach constructs a detection packet that includes a time to live indicator. The approach sends the detection packet from a virtual machine to one of multiple virtual network devices, wherein the virtual network device recognizes the detection packet based on the time to live indicator. The approach determines a network fault point based on receiving a notification packet from one of the multiple virtual network devices, and reports one of the multiple network interface devices that causes the network fault point.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a bottom isolation feature formed over the substrate. The semiconductor structure also includes a bottom semiconductor layer formed over the bottom isolation feature and nanostructures formed over the bottom semiconductor layer. The semiconductor structure also includes a source/drain structure attached to the nanostructures and covering a portion of the bottom isolation feature.

Abstract: A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

Abstract: A device includes a substrate, first and second gate structures, first and second hybrid fins, and first and second sidewalls. The first gate structure is over and surrounds a first vertical stack of nanostructures. The second gate structure is over and surrounds a second vertical stack of nanostructures. The second gate structure and the first gate structure extend along a first direction, and are laterally separated from each other in a second direction, the second direction being substantially perpendicular to the first direction. The first hybrid fin extends through and under the first gate structure and the second gate structure, the extending being along the second direction. The second hybrid fin is between the first gate structure and the second gate structure. The second hybrid fin has: a first sidewall that abuts the first gate structure; and a second sidewall that abuts the second gate structure.

Abstract: A method includes forming an active fin using a hard mask as an etching mask, wherein the active fin comprises a source region, a drain region, and a channel region, the hard mask remains over the active fin after etching the semiconductive substrate, and the hard mask has a first portion vertically overlapping the source region of the active fin, a second portion vertically overlapping the channel region of the active fin, and a third portion vertically overlapping the drain region of the active fin. A sacrificial gate is formed over the second portion of the hard mask and the channel region of the active fin. The first and third portions of the hard mask are etched. After etching the first and third portions of the hard mask, a gate spacer is formed extending along sidewalls of the sacrificial gate, and the sacrificial gate is replaced with a replacement gate.

Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure also includes a first bottom layer formed adjacent to the first nanostructures, and a first dielectric liner layer formed over the first bottom layer and adjacent to the first nanostructures. The semiconductor device structure further includes a first source/drain (S/D) structure formed over the first dielectric liner layer, and the first S/D structure is isolated from the first bottom layer by the first dielectric liner layer.