Patents by Inventor Zhi Cheng

Zhi Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240421219
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.
    Type: Application
    Filed: August 27, 2024
    Publication date: December 19, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
  • Publication number: 20240413200
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.
    Type: Application
    Filed: August 22, 2024
    Publication date: December 12, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Chuang-Han Hsieh, Kai-Lin Lee
  • Publication number: 20240413199
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.
    Type: Application
    Filed: August 22, 2024
    Publication date: December 12, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Chuang-Han Hsieh, Kai-Lin Lee
  • Patent number: 12132095
    Abstract: A method of fabricating a metal gate transistor includes providing a substrate. Then, a high-k dielectric layer is formed to cover the substrate. Later, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. After the ion implantation process, a polysilicon gate is formed on the high-k dielectric layer. Next, an interlayer dielectric layer is formed to cover the substrate and the polysilicon gate. Finally, the polysilicon gate is replaced by a metal gate.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: October 29, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Publication number: 20240335743
    Abstract: A method for playing back a virtual scene, a medium, an electronic device, and a computer program product. The method is used for an electronic device, and the method includes: receiving a recording instruction to record state data at beginning of the recording and change data during a recording process, of the virtual scene including at least one model (S10); and receiving a playback instruction, and playing back the virtual scene based on the state data and the change data, where, when the virtual scene is played back, an operation instruction is received and an operation result is displayed, and the operation instruction includes controlling at least one model of the virtual scene and/or generating an interaction event with at least one model of the virtual scene (S11). The method can control the playback virtual scene and/or interact with the playback virtual scene, so that user experience is improved.
    Type: Application
    Filed: January 24, 2022
    Publication date: October 10, 2024
    Inventor: Zhi Cheng
  • Patent number: 12112430
    Abstract: A method, system, and device for describing a relationship between objects in a three-dimensional virtual space, and a medium. The method of the present invention includes: for a first-level node under a three-dimensional virtual space node, determining that a position and a rotation direction of an object associated with the node are free; and for a node that is not a first-level node, obtaining a node type of the node and a node type of a parent node of the node, and determining that the object associated with the node maintains or does not maintain a relative position relative to an object associated with the parent node, and maintains or does not maintain a relative rotation direction relative to the object associated with the parent node.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: October 8, 2024
    Assignee: SHANGHAI LILITH TECHNOLOGY CORPORATION
    Inventors: Di Wu, Zhi Cheng
  • Patent number: 12107121
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: October 1, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Chuang-Han Hsieh, Kai-Lin Lee
  • Patent number: 12107157
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: October 1, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
  • Patent number: 12033327
    Abstract: Described herein are systems, methods, and instrumentalities associated with processing medical chest images such as chest X-ray (CXR) images. Segmentation models derived via a deep learning process are used to segment the chest images and obtain a rib segmentation result and a lung segmentation result for each image. The rib segmentation result may include a rib sequence identified in the image while the lung segmentation result may include one or more lung fields identified in the image. The quality of each chest image (e.g., whether the image reflects a breath-holding state of the patient) may then be determined based on whether a sufficient number of ribs in the rib segmentation result overlap with the lung fields in the lung segmentation result. The segmentation results may be obtained in a coarse-to-fine manner, e.g., by first determining a large rib area and then further segmenting the large rib area to identify each individual rib.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: July 9, 2024
    Assignee: Shanghai United Imaging Intelligence Co., Ltd.
    Inventors: Jie-Zhi Cheng, Qitian Chen
  • Publication number: 20240170301
    Abstract: A packaging substrate includes a circuit board defining a through groove. The circuit board includes an insulating body and a first wiring layer formed on the insulating body. A colloid is formed in the through groove. The packaging substrate further includes at least one lead. Each lead includes a lead body and a lead terminal connected to an end of the lead body. The lead terminal protrudes from the colloid. Another end of the lead body away from the lead terminal is electrically connected to the circuit board, and the colloid covering the lead body.
    Type: Application
    Filed: March 23, 2023
    Publication date: May 23, 2024
    Inventor: ZHI-CHENG LAN
  • Publication number: 20240119670
    Abstract: A method, system, and device for describing a relationship between objects in a three-dimensional virtual space, and a medium. The method of the present invention includes: for a first-level node under a three-dimensional virtual space node, determining that a position and a rotation direction of an object associated with the node are free; and for a node that is not a first-level node, obtaining a node type of the node and a node type of a parent node of the node, and determining that the object associated with the node maintains or does not maintain a relative position relative to an object associated with the parent node, and maintains or does not maintain a relative rotation direction relative to the object associated with the parent node.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 11, 2024
    Inventors: Di WU, Zhi CHENG
  • Publication number: 20240047554
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A protection layer is formed on the III-V compound barrier layer. An opening is formed penetrating through the protection layer in a vertical direction and exposing a part of the III-V compound barrier layer. A p-type doped III-V compound material is formed in the opening. A patterned barrier layer is formed on the p-type doped III-V compound material. A contact area between the patterned barrier layer and the p-type doped III-V compound material is less than an area of a top surface of the p-type doped III-V compound material.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 8, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Huai-Tzu Chiang, Chuang-Han Hsieh, Kai-Lin Lee
  • Publication number: 20240021702
    Abstract: An HEMT includes a first III-V compound layer, a second III-V compound layer, and a III-V compound cap layer. The second III-V compound layer is disposed on the first III-V compound layer. The III-V compound cap layer covers and contacts the second III-V compound layer. The composition of the III-V compound cap layer and the second III-V compound layer are different from each other. A first opening is disposed in the III-V compound cap layer. A first insulating layer includes two first insulating parts and two second insulating parts. The two first insulating parts cover a top surface of the III-V compound cap layer, and the two second insulating parts respectively contact two sidewalls of the first opening. A second opening is disposed between the two first insulating parts and between the two second insulating parts. A gate electrode is disposed in the second opening.
    Type: Application
    Filed: August 11, 2022
    Publication date: January 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Chuang-Han Hsieh, Huai-Tzu Chiang, Kai-Lin Lee
  • Publication number: 20230402537
    Abstract: A high electron mobility transistor (HEMT) device includes a substrate, a channel layer, a source, a drain, a buffer layer, and a plurality of amorphous regions. The channel layer is located above the substrate. The source is located on the channel layer. The drain is located on the channel layer. The buffer layer is located between the substrate and the channel layer. The plurality of amorphous regions are located in the buffer layer below the source and the drain.
    Type: Application
    Filed: July 13, 2022
    Publication date: December 14, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Huai-Tzu Chiang, Kai Lin Lee, Zhi-Cheng Lee, Chuang-Han Hsieh
  • Publication number: 20230375141
    Abstract: A flexible connection device of a Type IV cylinder and a container frame, comprising a damping block, an anti-rotation block, a bushing, upper and lower clamping blocks (43, 44), and the like. The damping block cooperates with the anti-rotation block to flexibly control the circumferential rotation of the Type IV cylinder; and the bushing is combined with the upper and lower clamping blocks (43, 44) to limit the axial motion of the Type IV cylinder. For the feature that the interface of a boss and a plastic liner/composite overwrap is prone to premature failure, by allowing axial movement of one end of the Type IV cylinder in the container within a small range, a binding force borne by the cylinder during expansion/contraction is released, and the damping block is squeezed to consume energy.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Inventors: Zhiping CHEN, You LI, Mengjie LIU, Zhi CHENG
  • Publication number: 20230361207
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
  • Publication number: 20230300590
    Abstract: A fail-safe on-board unit, a movable device, and a control method for a vehicle which will automatically and reliably broadcast a distress signal to a rescue center in the event of accident includes in the on-board unit a first subscriber identity module (SIM), a second SIM, a main processor, a modem, a radio frequency (RF) switch module, and an antenna module with several antennas. The main processor selects the first SIM and / or the second SIM to make a call to generate a baseband signal, and outputs the baseband signal to the modem, the modem converts the baseband signal into an RF signal, and outputs the RF signal to the RF switch module to transmit outward via one or more antennas of the antenna module. The on-board unit has a wider network coverage to ensure higher success rate of emergency calls.
    Type: Application
    Filed: February 6, 2023
    Publication date: September 21, 2023
    Inventors: FENG-YUAN LI, ZHI-CHENG YU, XIAO-MIN LIANG
  • Patent number: 11753786
    Abstract: A fixed permeable breakwater which also serves as a wave power generating device is provided and includes a structure, a structure fixing device and a wave-activated generator set, the structure is connected with a seabed through the structure fixing device, holes are arranged on an outer side of upper arc vertical walls of the structure, and spiral vane sets are placed in the holes; a spiral-gear generator is installed on the horizontal bearing plate, and waves push the spiral vane sets to rotate, and then push the spiral-gear generator to generate electricity.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: September 12, 2023
    Assignee: Ludong University
    Inventors: Xueyan Li, Chunyi Xiu, Zhenhua Zhang, Zhi Cheng, Yujie Meng, Jinke Li
  • Patent number: 11749748
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: September 5, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
  • Patent number: D1072813
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: April 29, 2025
    Assignee: Nanning FuLian FuGui Precision Industrial Co., Ltd.
    Inventors: Zhi-Cheng Yu, Xiao-Min Liang