Abstract: Methods for treating landfill leachate taught herein comprise: (a) coagulatively settling leachate; (b) filtering the resultant supernatant liquid through multistage cartridges; (c) filtering the filtered liquid by reverse osmosis; and (d) treating the resultant liquid with chlorine-based oxidant. These methods provide the advantages of efficient wastewater treatment, compact equipment size, short process flow, and low startup and operational costs.

Abstract: Described are methods and circuits for identifying defective device layers and localizing defects. Production PLD tests extract statistically significant data relating failed interconnect resources to the associated conductive metal layer. Failure data thus collected is then analyzed periodically to identify layer-specific problems. Test circuits in accordance with some embodiments employ interconnect resources heavily weighted in favor of specific conductive layers to provide improved layer-specific failure data. Some such test circuits are designed to identify open defects, while others are designed to identify short defects.

Abstract: Methods for monitoring and improving the fabrication process of integrated circuits using configurable devices are described. In one aspect, the method includes instantiating a test pattern on one or more configurable devices fabricated using the fabrication process, identifying an underperforming region of the configurable devices, and determining if the underperforming region is layout sensitive. At least one of the fabrication process and the layout of the configurable device can then be adjusted based on the determination. In some embodiments, the configurable device may be a programmable logic device, such as a field programmable logic array.

Abstract: Method and apparatus are disclosed for analyzing defect data produced in testing a semiconductor chip from a logic design. In various embodiments, input for processing is a first inspection data set that identifies a first set of physical locations that are associated with defects detected during fabrication of the chip. Also input is a second test data set that includes one or more identifiers associated with failing circuitry in the chip. A second set of physical locations is determined from the one or more identifiers of failing circuitry, hierarchical relationships between blocks of the design, and placement information associated with the blocks. Each of the one or more identifiers is associated with at least one of the blocks. Correspondences are identified between physical locations in the first inspection data set and the second set of physical locations.

Abstract: Disclosed is a one step method for preparing a ?-substituted sulfide by treating a ?-halosulfide with a nucleophile in water.

Abstract: Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.

Abstract: The invention provides compositions and methods for inhibiting degradation of p53, thereby enhancing p53-mediated tumor suppressor activity.

Abstract: Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.

Abstract: Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.

Abstract: A support structure for reducing shock to a camera module for use in a mobile communications terminal is provided. The mobile communication terminal comprises a camera case for housing the camera module, the support structure comprising a first projection protruding from an inner surface of the camera case, the first projection in operational relationship with a first receiving cavity formed in the camera module to firmly hold the camera module inside the camera case and prevent the camera module from moving in relationship to the camera case.

Abstract: A mobile communication terminal with an integrated photographic apparatus is disclosed. The photographic apparatus is rotatively connected to the terminal. Further, a magnet, which generates a flux, is connected to the photographic apparatus. A magnetic flux sensor is also connected to the terminal so that an image produced by the photographic apparatus is inverted when the magnetic flux sensor detects the magnetic flux. Rotation of the photographic apparatus at a predetermined angle approximates the magnet to the magnetic flux detecting sensor.

Abstract: Described are methods and circuits for identifying defective device layers and localizing defects. Production PLD tests extract statistically significant data relating failed interconnect resources to the associated conductive metal layer. Failure data thus collected is then analyzed periodically to identify layer-specific problems. Test circuits in accordance with some embodiments employ interconnect resources heavily weighted in favor of specific conductive layers to provide improved layer-specific failure data. Some such test circuits are designed to identify open defects, while others are designed to identify short defects.

Abstract: Disclosed is a mobile communication terminal with an integrated photographic apparatus having an optical zoom function. The terminal comprises of a body, a display, one or more input devices to enter terminal and photographic commands, and a photographic apparatus having a zoom function. The photographic apparatus comprises of a housing in which a lens, lens cap, and camera are situated. A rotation handle on the exterior surface of the camera can be used to manually manipulate the distance between the camera and the lens, thereby zooming in and out on a subject to be photographed. Alternatively, a motor and driving means can be installed to adjust the distance between the camera and the lens. A user can use the command functions of the terminal to input commands to the motor to effectuate zooming. Furthermore, a sensor installed in the terminal can be used for automated zooming.

Abstract: Disclosed is a one step method for preparing a &bgr;-substituted sulfide by treating a &bgr;-halosulfide with a nucleophile in water.

Abstract: FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can execute the design accurately even with the localized defect. The FPGA will be marked as suitable for that design if it passes the test. If the FPGA is found to be unsuitable for one design, additional designs may be tested. Thus, a FPGA manufacturer can sell FPGAs that are normally discarded. As a result, the price of these FPGAs could be set significantly low.

Abstract: Disclosed is a one step method for preparing a 1,2,3-triazole carboxylic acid by treating an azide with a &bgr;-ketoester in the presence of a base.

Abstract: Disclosed is a one step method for preparing a 1,2,3-triazole carboxylic acid by treating an azide with a &bgr;-ketoester in the presence of a base.

Abstract: A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.

Abstract: Novel therapeutic lipid constructs comprising a polymerized liposome, an anti-cell surface targeting agent, and a radiotherapeutic metal ion are disclosed.

Abstract: A wireless transmission circuit enabling adjustable RF transmission power includes a signal modulator-oscillator stage, a power-amplifier stage, and a filter circuit. A bias voltage condition of an output transistor of the signal modulator-oscillator stage or the power-amplifier stage is adjustable via a bias control circuit, so as to adjust an output power of the signal modulator-oscillator stage or the power-amplifier stage. When a wireless input device employing the wireless transmission circuit is used to work within a short distance, a lower transmission power may be selected for it. And, when the same input device is used to work at a remote location, a higher transmission power may be selected to achieve the remote transmission. In this manner, the wireless input device may have effectively extended battery life.