Abstract: A wireless transmission circuit enabling adjustable RF transmission power includes a signal modulator-oscillator stage, a power-amplifier stage, and a filter circuit. A bias voltage condition of an output transistor of the signal modulator-oscillator stage or the power-amplifier stage is adjustable via a bias control circuit, so as to adjust an output power of the signal modulator-oscillator stage or the power-amplifier stage. When a wireless input device employing the wireless transmission circuit is used to work within a short distance, a lower transmission power may be selected for it. And, when the same input device is used to work at a remote location, a higher transmission power may be selected to achieve the remote transmission. In this manner, the wireless input device may have effectively extended battery life.

Abstract: A wireless transmission circuit enabling modulation of RF power amplification includes a signal processing circuit for outputting a signal that is modulated and then amplified at a cascade power amplification circuit including a plurality of power stages, and is then wirelessly transmitted to and received by a computer system. The wireless transmission circuit includes at least a power-setting unit for controlling a specific number of power stages included in the power amplification circuit to be used in the power amplification of the modulated signal. When a wireless input device employing the wireless transmission circuit is used within a short transmission distance, a lower transmission power is selected via the power-setting unit; and when the wireless input device is used at a long transmission distance, a higher transmission power may be selected to achieve the remote transmission. The wireless input device could therefore have extended battery life.

Abstract: Novel therapeutic lipid constructs comprising a polymerized liposome, an anti-cell surface targeting agent, and a radiotherapeutic metal ion are disclosed.

Abstract: FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can execute the design accurately even with the localized defect. The FPGA will be marked as suitable for that design if it passes the test. If the FPGA is found to be unsuitable for one design, additional designs may be tested. Thus, a FPGA manufacturer can sell FPGAs that are normally discarded. As a result, the price of these FPGAs could be set significantly low.

Abstract: The invention provides compositions and methods for inhibiting degradation of p53, thereby enhancing p53-mediated tumor suppressor activity.

Abstract: Therapeutic and imaging agents which are comprised of a targeting entity, a therapeutic or treatment entity and a linking carrier are provided. The linking carrier imparts additional advantages to the therapeutic agents, which are not provided by conventional linking methods. Preferred agents of the present invention comprise a lipid construct, vesicle, liposome, or polymerized liposome. In some cases, the therapeutic or treatment entity is a radioisotope, chemotherapeutic agent, prodrug, toxin, or gene encoding a protein that exhibits cell toxicity. Preferably, the agent is further comprised of a stabilizing entity that imparts additional advantages to the therapeutic or imaging agent.

Abstract: A reticle that is modified to prevent bridging of the masking material (e.g., chrome) between portions of the lithographic mask pattern during an integrated circuit fabrication process. According to a first aspect, the modification involves electrically connecting the various portions of the lithographic mask pattern that balance charges generated in the portions during fabrication processes. In one embodiment, sub-resolution wires that extend between the lithographic mask pattern portions facilitate electrical conduction between the mask pattern portions, thereby equalizing dissimilar charges. In another embodiment, a transparent conductive film is formed over the lithographic mask pattern to facilitate conduction. In accordance with a second aspect, the modification involves separating the various portions of the lithographic mask pattern into relatively small segments by providing sub-resolution gaps between the various portions, thereby minimizing the amount of charge that is generated on each portion.

Abstract: An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects.

Abstract: An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects.

Abstract: An arrangement and method for detecting sequential processing effects on products to be manufactured in a manufacturing process orders a first set of the products in a first specified processing sequence for a first process step in the manufacturing process. In order to prevent any positional trend created at one process step from being carried over into the next process step, the first set of the products is re-ordered into a second, different specified processing sequence for a second process step in the manufacturing process. Data regarding responses of the first set of the products to the process steps are extracted. The extracted data are correlated with the first and second processing sequences and data analysis is performed on the correlated extracted data.

Abstract: An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects.

Abstract: An arrangement and method for detecting sequential processing effects on devices to be manufactured in a manufacturing process extracts data regarding responses of the devices to a process step in the manufacturing process and data regarding a processing sequence of the devices in that process step. The extracted data is refined before analysis and control chart rules are then applied to the refined data. These control chart rules detect whether there are any unusual processing effects caused by the sequence of processing of the devices in any one of the individual processing steps. Application of control chart rules to the refined data allows an automatic determination of whether there are any rule violations. One or more control charts which have a rule violation are automatically generated when it is determined that there is a rule violation. Process engineers may then use the automatically generated charts to direct their efforts at improving the manufacturing process.

Abstract: An arrangement and method for detecting sequential processing effects on products to be manufactured in a manufacturing process orders a first set of the products in a first specified processing sequence for a first process step in the manufacturing process. In order to prevent any positional trend created at one process step from being carried over into the next process step, the first set of the products is re-ordered into a second, different specified processing sequence for a second process step in the manufacturing process. Data regarding responses of the first set of the products to the process steps are extracted. The extracted data are correlated with the first and second processing sequences and data analysis is performed on the correlated extracted data.

Abstract: An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects.

Abstract: Diaziridinylpolyamines useful as anti-cancer agents; compositions containing the same, and methods of using the same for the treatment of cancer are described.

Abstract: A real-time in-line defect disposition and yield forecasting system for a semiconductor wafer having layer containing devices includes an in-line fabrication inspection tool, a design review station, and a yield management station. The in-line fabrication inspection tool inspects at least two layers of the semiconductor wafer and produces first information including particle size, particle location and number of particles introduced therein for each of these layers. The design review station inspects the layers of the semiconductor wafer and produces second information including layouts of each of the layers. The yield management station is operatively connected to the in-line fabrication inspection tool and to the design review station. The yield management station retrieves the first information and the second information from the in-line fabrication inspection tool and from the design review station.