Abstract: The present disclosure relates to the field of regulation of plant performance genes, in particular to a pectin methylesterase inhibitor gene GhPMEI39 and application of its encoded protein. The gene sequence of the pectin methylesterase inhibitor gene GhPMEI39 is shown in SEQ ID NO:1. According to the present disclosure, a public database is used to screen target genes, primers are designed to clone the target genes, its cotton transgenic materials and Arabidopsis thaliana transgenic materials are constructed, and plant development phenotypes after overexpression and constitutive expression of pectin methylesterase inhibitor protein are analyzed, and the role of the pectin methylesterase inhibitor gene GhPMEI39 in related functions such as plant flowering and inflorescence morphology is verified.

Abstract: Embodiments of the present application provide a battery, a power consumption apparatus, and a method and an apparatus for preparing a battery. The battery includes a plurality of battery cells arranged in a first direction. Each battery cell is provided with a pressure relief mechanism, configured to be actuated when internal pressure or temperature of the battery cell reaches a threshold value, to relieve the internal pressure. The battery further includes a protecting plate, the protecting plate is attached to a surface of the battery cells arranged in the first direction. The protecting plate is provided with a plurality of openings, and an opening is provided corresponding to the pressure relief mechanism of a battery, to expose the pressure relief mechanism via the opening. Two openings corresponding to pressure relief mechanisms of two adjacent battery cells are provided in a staggered manner in the first direction.

Abstract: A battery includes battery units arranged side by side along a first direction, each including at least two battery cells arranged along a second direction perpendicular to the first direction. The battery cell includes a body portion, a gap is formed between the body portions of at least two adjacent battery cells in the battery unit. At least one of the adjacent battery cells includes an electrode terminal protruding from the body portion and located in the gap and configured to be electrically connected to the other battery cell. The battery further includes a sampling member at least partially located in the gap and including a sampling portion and a lead-out portion. The sampling portion is electrically connected to the electrode terminal and is configured to collect an electrical signal of the battery cell.

Abstract: A method and system for optimizing live migration of a virtual machine (VM) from a source server to a destination server where hardware accelerator virtualization is used. Hardware accelerator performance data is obtained while executing a workload on a virtual function at the source server. It is determined whether to transfer the workload from the source server to the destination server based on the hardware accelerator performance data. The workload is transferred from the source server to the destination server based on the determination. The hardware accelerator performance data may include an amount of output data the workload generates and an amount of input data to the workload. The hardware accelerator may be a graphics processing unit (GPU), and the workload may be a GPU workload.

Abstract: A method of this disclosure may include performing a named entity recognition on text information related to requirements for a wireframe by a first artificial intelligence (AI) model, so as to extract entities and relations of the entities from the text information. The method may further comprise inputting the extracted entities and relations to a second AI model to generate the wireframe, wherein the second AI model is trained so that a difference between resultant relations of the entities of the generated wireframe and the extracted relations of the entities from the first AI model is decreased.

Abstract: A battery includes a plurality of battery units arranged in parallel in one layer or a plurality of layers, a plate disposed on one side of the battery units in the one layer or in one of the plurality of layers, and a protective cover having a top wall and two side walls disposed at two ends of the top wall and connected to the top wall. The protective cover fixes at least one of the battery units each separately on the plate.

Abstract: Described are a method and apparatus for controlling the power consumption of a terminal, and a storage medium. The method includes: recording the number of times a connection between a terminal and an auxiliary cell group fails, and where the number of times is greater than a preset threshold value, controlling, on the basis of a power consumption adjustment policy, the terminal to disable a dual-connection mode, wherein the terminal can support the dual-connection mode, and in the dual-connection mode, the terminal communicates with both a first base station and a second base station, the second base station being an auxiliary base station, and the auxiliary cell group being a group of serving cells associated with the auxiliary base station.

Abstract: A display substrate and a display device are provided. In the display substrate, a first signal line transmitting a first scan signal extends along a first direction and a second signal line transmitting a data signal extends along a second direction; the data writing transistor transmits the data signal to the driving transistor under control of the first scan signal, the first scan signal is transmitted on the first signal line, and the data signal is transmitted on the second signal line; the driving transistor controls magnitude of a driving current according to the data signal; the channel region at least partially overlaps with the gate electrode; a planar shape of the channel region of the driving transistor is a strip shape extending along the second direction; the light emitting device receives the driving current and is driven by the driving current to emit light.

Abstract: The display substrate includes: a display area and a bezel area, the display area including a first display area and a second display area; first light emitting devices in the first display area and second light emitting devices in the second display area; first pixel drive circuits in the bezel area and second pixel drive circuits in the second display area, the first pixel drive circuits are connected to the first light emitting devices, and the second pixel drive circuits are connected to the second light emitting devices; and shift registers in the bezel area, one shift register is connected with the first pixel driving circuits connected with one row of the first light emitting devices and the second pixel driving circuits connected with one row of the second light emitting devices.

Abstract: Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.

Abstract: This disclosure provides a display panel and a display device. The display panel includes a light-transmitting area, a first transitional display area, a first main display area and a second main display area, and further includes a first light-emitting unit in the light-transmitting area, a first pixel driving circuit in the first transitional display area for providing a driving current to the first light-emitting unit, a first signal line extending along the column direction in the first main display area, a second signal line extending along the column direction in the second main display area, and a third signal line. The third signal line and the first signal line are in different conductive layers, the third signal line and the second signal line are in different conductive layers, and the third signal line is connected with the first signal line and the second signal line through via holes respectively.

Abstract: A deep learning-based Java program internal annotation generation method and system is provided. The method includes acquiring items with a Stars number ranked in the top, and extracting corresponding internal annotations and method statement lists; obtaining an <annotation, target code> pair; selecting an annotation in a Verb-dobj form; obtaining a code context associated with a target code segment; preprocessing the annotation, the target code, and the context to obtain a triplet dataset; randomly dividing the constructed dataset into a training set, a validation set, and a test set, and constructing an encoder-decoder network at the same time; enabling the training set in division to be used for model training, performing evaluation on the validation set to obtain a model with the best effect on the validation set as a target model; and predicting data in the test set with the obtained target model to generate a predicted annotation.

Abstract: An embodiment of a semiconductor package apparatus may include technology to manage one or more virtual graphic processor units, and co-schedule the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions. Other embodiments are disclosed and claimed.

Abstract: A method, device and computer readable medium for service chain is provided. Dynamic service chain is achieved and the service chain request is transmitted from the application. The device determines the service chain based on a profile of the application. Further, implicit service chain subscribing is also achieved. Thus, a more flexible service chain is achieved. Further, management of service chain related to NF service is also achieved.

Abstract: A pixel circuit and a driving method therefor, and a display device are provided. The pixel circuit includes a driving subcircuit, a first light emitting control subcircuit, a second light emitting control subcircuit, a first switching subcircuit, a second switching subcircuit, a third switching subcircuit, a fourth switching subcircuit and an energy storage subcircuit.

Abstract: A thin film transistor includes a base, a first electrode, an active pattern, a gate insulating layer, a gate and a second electrode. The active pattern includes a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern. A material of one of the first semiconductor pattern and the third semiconductor pattern includes a semiconductor material and N-type doped ions, and a material of another of the first semiconductor pattern and the third semiconductor pattern includes the semiconductor material and P-type doped ions. An orthogonal projection of the gate on the base is non-overlapping with an orthogonal projection of the active pattern on the base.

Abstract: Disclosed is a display substrate including a base substrate, which includes first and second display regions, and at least one first data line. The first display region includes first and second sub-display regions located on opposite sides of the second display region along a first direction; and a third sub-display region located on at least one side of the second display region along a second direction. The first data line includes a first sub-data line located in the first sub-display region and connected with a pixel circuit of the first sub-display region, a second sub-data line located in the second sub-display region and connected with a pixel circuit of the second sub-display region, and a third sub-data line which is connected with the first and second sub-data lines, located in the third sub-display region, and connected with at least one second pixel circuit of the third sub-display region.

Abstract: A printing head and a method for applying a correction for mounting deviation of light-emitting chips are provided. The printing head includes a plurality of light-emitting chips. Each light-emitting chip includes a plurality of primary light-emitting elements that are continuously arranged. At least one of two adjacent light-emitting chips further includes at least one spare light-emitting element continuously and linearly arranged after the primary light-emitting elements. If the two adjacent light-emitting chips are both at a target mounting position, first N light-emitting units of one of the two light-emitting chips respectively face to first N light-emitting units of the other one of the two light-emitting chips, where N?1. Each two of the light-emitting units facing to each other form a group. One of the two light-emitting units in each of the groups is set to a light emission disabled state.

Abstract: Systems and techniques for wireless implantable devices, for example implantable biomedical devices employed for biomodulation. Some embodiments include a biomodulation system including a non-implantable assembly including a source for wireless power transfer and a data communications system, an implantable assembly including a power management module configured to continuously generate one or more operating voltage for the implantable assembly using wireless power transfer from the non-implantable assembly, a control module operably connected to at least one communication channel and at least one stimulation output, the control module including a processor unit to process information sensed via the at least one communication channel and, upon determining a condition exists, to generate an output to trigger the generation of a stimulus.

Abstract: A memory management method for a memory storage device is provided. The memory management method includes: detecting effective information of at least one operation event performed by the memory storage device in a first mode; and adjusting a threshold value according to the effective information. The threshold value is configured to determine whether to instruct the memory storage device to enter the first mode.