Abstract: A microchannel flat tube applicable in a microchannel heat exchanger includes a flat tube body and a row of channels. The row of channels is arranged in the flat tube body along a width direction. The row of channels extends through the flat tube body along a length direction. A cross-section of each channel includes a first width in the width direction and a first height in a thickness direction. The row of channels at least includes a first group of first channels, a second group of second channels and a third group of third channels along the width direction. The first widths of the first channels, the second channels and the third channels decrease at a fixed value, thereby facilitating the control of the thickness of the microchannel flat tube and improving the heat exchange efficiency.

Abstract: A valid node management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: establishing a valid node management table corresponding to a first physical management unit; storing valid node management data in the valid node management table, wherein the valid node management data reflects a distribution status of a valid node in the first physical management unit; receiving an operation command from a host system, wherein the operation command is configured to change a data storage status of the first physical management unit; and updating the valid node management data in the valid node management table in response to the operation command.

Abstract: A method for realizing predistortion compensation processing for 5G NR in-band modulated signals includes configuring the modulator to output a continuous wave signal, switch the output frequency interval of the signal to be consistent with the 5G NR subcarrier bandwidth, and record the power value P0 corresponding to the current frequency through the power meter. The power measurement difference between all points and P0 is calculated and performs normalization, and generates a compensated channel impulse response after shaping filtering; converts it into a power compensation factor in the time domain; performs inverse Fourier transform to generate I and Q baseband signals; generates compensated baseband data; the generated baseband data is filtered, and an analog zero intermediate frequency signal is generated, which is input to the broadband demodulator for frequency conversion modulation of the 5G NR broadband signal. The method operates without the need to modify the device circuit in the channel.

Abstract: An operation method of a direct memory access (DMA) circuit comprising a buffer circuit and two channels includes following steps: determining first and second start addresses from the buffer circuit respectively according to first and second read requests of first and second channels that respectively correspond to first and second data; determining a read address according to the first start address and a read count; reading a first part of the first data from the buffer circuit according to the read address and updating the read count; reading at least one part of the second data from the buffer circuit according to the second start address after reading the first part of the first data; updating the read address according to the first start address and the updated read count; and reading a second part of the first data from the buffer circuit according to the updated read address.

Abstract: A deep learning-based Java program internal annotation generation method and system is provided. The method includes acquiring items with a Stars number ranked in the top, and extracting corresponding internal annotations and method statement lists; obtaining an <annotation, target code> pair; selecting an annotation in a Verb-dobj form; obtaining a code context associated with a target code segment; preprocessing the annotation, the target code, and the context to obtain a triplet dataset; randomly dividing the constructed dataset into a training set, a validation set, and a test set, and constructing an encoder-decoder network at the same time; enabling the training set in division to be used for model training, performing evaluation on the validation set to obtain a model with the best effect on the validation set as a target model; and predicting data in the test set with the obtained target model to generate a predicted annotation.

Abstract: The present application provides a combinable weight plate, which relates to the field of fitness equipment, and includes a plate body, a limiting assembly and an engaging assembly. The limiting assembly and the engaging assembly are arranged in the plate body. The engaging assembly is used to engage and connect the two plate bodies, and the limiting assembly is used to restrict the relative rotation of the two engaged and connected plate bodies. The present application also provides a weight adjustable kettle bell. The present application also provides a weight adjustable dumbbell. The present application also provides a weight adjustable barbell.

Abstract: A display substrate and a display device are provided. In the display substrate, a first signal line transmitting a first scan signal extends along a first direction and a second signal line transmitting a data signal extends along a second direction; the data writing transistor transmits the data signal to the driving transistor under control of the first scan signal, the first scan signal is transmitted on the first signal line, and the data signal is transmitted on the second signal line; the driving transistor controls magnitude of a driving current according to the data signal; the channel region at least partially overlaps with the gate electrode; a planar shape of the channel region of the driving transistor is a strip shape extending along the second direction; the light emitting device receives the driving current and is driven by the driving current to emit light.

Abstract: A compound of formula (I) capable of inhibiting plasmin activity, delaying fibrinolysis, and having coagulation and hemostatic activity, pharmaceutically acceptable salts, hydrates, isomers, prodrugs and mixtures thereof, wherein X, and R1 to R5 are as defined in the description.

Abstract: A method includes performing pre-treating, comprising fire-roasting or wet-washing, on the processed aluminum scraps of aeronautical aluminum alloy. The method further includes performing pressing formation on the pre-treated processed aluminum scraps of aeronautical aluminum alloy to form block-shaped aluminum scraps. The method further includes performing oxygen-controlled smelting on the block-shaped aluminum scraps in a smelting furnace to form aluminum alloy melt. The method further includes performing casting on the aluminum alloy melt to obtain an aluminum alloy product of meeting component requirements of aeronautical aluminum alloy.

Abstract: A data writing method, a memory storage device, and a memory control circuit unit are disclosed. The method includes the following. A write command is received from a host system. The write command instructs storing of first data belonging to a first logical unit. In response to the first data being first type data, the first data is stored in a first type physical unit according to the write command and first count information corresponding to a first logical range is updated. The first logical unit belongs to the first logical range. In response to the first count information meeting a preset condition, the first data is moved from the first type physical unit to a second type physical unit.

Abstract: A pixel circuit, a driving method for same, and a display apparatus are provided. The pixel circuit includes a driving sub-circuit, a writing sub-circuit, a compensation sub-circuit, a first reset sub-circuit, an emitting element. The driving sub-circuit provides a driving current for a third node under control of signals of first and second nodes. The writing sub-circuit writes a signal of the data signal terminal into the second node under control of a signal of a second scanning signal terminal. The first reset sub-circuit writes an initial voltage signal of a first initial signal terminal into the third node under control of a first scanning signal terminal and a first emitting control signal terminal. The compensation sub-circuit writes the initial voltage signal of the third node into the first node under control of a third scanning signal terminal, compensates the first node under control of the third scanning signal terminal.

Abstract: A valid node management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: establishing a valid node management table corresponding to a first physical management unit; storing valid node management data in the valid node management table, wherein the valid node management data reflects a distribution status of a valid node in the first physical management unit; receiving an operation command from a host system, wherein the operation command is configured to change a data storage status of the first physical management unit; and updating the valid node management data in the valid node management table in response to the operation command.

Abstract: This disclosure provides a display panel and a display device. The display panel includes a light-transmitting area, a first transitional display area, a first main display area and a second main display area, and further includes a first light-emitting unit in the light-transmitting area, a first pixel driving circuit in the first transitional display area for providing a driving current to the first light-emitting unit, a first signal line extending along the column direction in the first main display area, a second signal line extending along the column direction in the second main display area, and a third signal line. The third signal line and the first signal line are in different conductive layers, the third signal line and the second signal line are in different conductive layers, and the third signal line is connected with the first signal line and the second signal line through via holes respectively.

Abstract: The present disclosure relates to the field of regulation of plant performance genes, in particular to a pectin methylesterase inhibitor gene GhPMEI39 and application of its encoded protein. The gene sequence of the pectin methylesterase inhibitor gene GhPMEI39 is shown in SEQ ID NO:1. According to the present disclosure, a public database is used to screen target genes, primers are designed to clone the target genes, its cotton transgenic materials and Arabidopsis thaliana transgenic materials are constructed, and plant development phenotypes after overexpression and constitutive expression of pectin methylesterase inhibitor protein are analyzed, and the role of the pectin methylesterase inhibitor gene GhPMEI39 in related functions such as plant flowering and inflorescence morphology is verified.

Abstract: A replacement node replaces a failed node and a baseboard management controller (BMC) for the replacement node generates a nonce code that is accessible to an authenticated user. An edge management node receives the nonce code from the user and sends a maintenance token to a BMC of a peer node in an edge cluster, wherein the peer nodes BMCs within the cluster are in a BMC federation that included the failed node BMC and have access to a BMC configuration for the failed node. The management node sends the token and the nonce code to the replacement node BMC for authentication of the token. The peer node BMC sends the token received from the management node to the replacement node BMC for authentication of the peer node BMC. The authenticated peer node BMC may then deploy the BMC configuration to the replacement node BMC.

Abstract: A battery includes battery units arranged side by side along a first direction, each including at least two battery cells arranged along a second direction perpendicular to the first direction. The battery cell includes a body portion, a gap is formed between the body portions of at least two adjacent battery cells in the battery unit. At least one of the adjacent battery cells includes an electrode terminal protruding from the body portion and located in the gap and configured to be electrically connected to the other battery cell. The battery further includes a sampling member at least partially located in the gap and including a sampling portion and a lead-out portion. The sampling portion is electrically connected to the electrode terminal and is configured to collect an electrical signal of the battery cell.

Abstract: Embodiments of the present application provide a battery, a power consumption apparatus, and a method and an apparatus for preparing a battery. The battery includes a plurality of battery cells arranged in a first direction. Each battery cell is provided with a pressure relief mechanism, configured to be actuated when internal pressure or temperature of the battery cell reaches a threshold value, to relieve the internal pressure. The battery further includes a protecting plate, the protecting plate is attached to a surface of the battery cells arranged in the first direction. The protecting plate is provided with a plurality of openings, and an opening is provided corresponding to the pressure relief mechanism of a battery, to expose the pressure relief mechanism via the opening. Two openings corresponding to pressure relief mechanisms of two adjacent battery cells are provided in a staggered manner in the first direction.

Abstract: A method of this disclosure may include performing a named entity recognition on text information related to requirements for a wireframe by a first artificial intelligence (AI) model, so as to extract entities and relations of the entities from the text information. The method may further comprise inputting the extracted entities and relations to a second AI model to generate the wireframe, wherein the second AI model is trained so that a difference between resultant relations of the entities of the generated wireframe and the extracted relations of the entities from the first AI model is decreased.

Abstract: A method and system for optimizing live migration of a virtual machine (VM) from a source server to a destination server where hardware accelerator virtualization is used. Hardware accelerator performance data is obtained while executing a workload on a virtual function at the source server. It is determined whether to transfer the workload from the source server to the destination server based on the hardware accelerator performance data. The workload is transferred from the source server to the destination server based on the determination. The hardware accelerator performance data may include an amount of output data the workload generates and an amount of input data to the workload. The hardware accelerator may be a graphics processing unit (GPU), and the workload may be a GPU workload.