Abstract: Aspects relate to managing a device-to-device communication link via radio resource control (RRC) layer signaling. In an example operation, a first wireless communication device establishes a unicast link with a second wireless communication device over a device-to-device communication interface and determines that the unicast link is to be reconfigured with at least one updated parameter. The first wireless communication device then sends a link reconfiguration request to the second wireless communication device via a first RRC message over the communication interface. The first RRC message includes the at least one updated parameter. The first wireless communication device receives a link reconfiguration response from the second wireless communication device via a second RRC message over the communication interface based on the link reconfiguration request and determines whether to reconfigure the unicast link using the at least one updated parameter based on the received link reconfiguration response.

Abstract: Certain aspects of the present disclosure are generally directed to techniques for selecting a configuration for communication using vehicle to everything (V2X) type communication protocol. Certain aspects provide a method for wireless communication by a user-equipment (UE). The method generally includes determining one or more parameters corresponding to quality of service (QoS) information for communication of data using a V2X communication protocol, reporting the one or more parameters by transmitting a first message, receiving a second message indicating configuration information corresponding to the communication of the data using the V2X communication protocol, and communication the data based on the configuration information.

Abstract: Methods, systems, and devices for wireless communications are described in which two or more UEs of a wireless communications system may establish a sidelink connection. A first UE that is initiating sidelink communications may evaluate whether the sidelink connection can support a quality of service (QoS) for a data flow prior to admitting the data flow. The first UE may evaluate a link quality with one or more other UEs that are to use the data flow on the sidelink connection, evaluate system congestion of time/frequency resources that are available for the sidelink connection, or any combinations thereof, and admit the data flow based on the evaluation. A link quality of the sidelink connection may be determined based on a type of communication associated with the data flow, such as unicast communications with one other UE, multicast communications with multiple other UEs, or broadcast transmissions to multiple UEs.

Abstract: The present application relates to apparatus, systems, and methods to provide a service based interface in wireless communication systems.

Abstract: Methods, systems, and devices for wireless communication are described. One method for wireless communication at a first device includes receiving a multicast packet from a second device, decoding control header information in the received multicast packet, determining that a decoding procedure associated with a payload of the received multicast packet is unsuccessful and transmitting a negative acknowledgement (NACK) based at least in part on the determining. The method also includes retrieving a list of transmitter identifiers. In some cases, transmitting the NACK is based at least in part on the list of transmitter identifiers. The method further includes determining a transmitter identifier associated with the multicast packet and determining that the transmitter identifier is present in the list of transmitter identifiers.

Abstract: The disclosed computer-implemented method may include extracting, from a baseline video file, metadata that identifies at least one characteristic of the baseline video file, creating, using the extracted metadata as a framework, a template for remixing the baseline video file with new content, obtaining at least one new item of content, and creating, using the template, a remixed version of the baseline video file by replacing at least one original item of content in the baseline video file with the new item of content. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A fully automated chemilumiescence immunoassay analyzer, including a sample and reagent receiving device for receiving a sample and a reagent, a dispensing device for aspirating and discharging the sample and the reagent, a mixing device for mixing the sample and the reagent in a reaction vessel, an incubation and luminescence detection device for incubation and luminescence detection, a magnetic separation cleaning device for separation cleaning an analyte and impurities in the reaction vessel, a reaction vessel grasping device for transferring the reaction vessel, and a liquid path device. The fully automated chemiluminescence immunoassay analyzer has a simple structure and is convenient to operate, and also reduce the overall size such that the footprint thereof is small and the production cost is reduced, so that the analyzer is easy to achieve miniaturization, and is convenient for an operator to use.

Abstract: A circuit for a multiplexer includes a pair of NAND gates with outputs coupled to an OAI gate constructed from a complementary circuit formed from solid state devices. A current flow controller formed from solid state devices is coupled to one of the NAND gates. When activated the controller inhibits the flow of current through the NAND gate and a portion of the OAI gate to which the controller is connected. As a consequence, leakage power is not consumed within the multiplexer. Several of the applications in which the circuit is used are also demonstrated in the specification.

Abstract: Methods and apparatuses to measure temperatures of integrated circuits are disclosed. New circuit arrangements for measuring temperature using various types of integrated circuit sensor elements are discussed. Embodiments comprise methods and apparatuses arranged to measure temperature based upon current leakage rates of different integrated circuit sensor elements. The methods and apparatuses generally involve using a pulse module to generate a charge for the integrated circuit elements. In these method and apparatus embodiments, one or more elements form a decay module to sense when the voltage decays to a threshold value. The method and apparatus embodiments may also have a module to calculate or infer a temperature from the rate of the voltage decay.

Abstract: Embodiments that decrease power consumption of interconnecting devices in integrated circuits are disclosed. Embodiments reduce power consumption in integrated circuits by generating full and reduced swing signals at an output of a driver module in response to a control signal during and deactivating one or more elements to conserve power after an input signal remains unchanged for a period of time. Another embodiment reduces power consumption in a circuit, the embodiment comprising a swing module coupled with a swing selector and an output controller. The swing module may generate full or low swing signals depending on the state of the swing selector. The output controller may increase the output impedance of the swing module after an input signal to the swing module remains unchanged for a quantity of time. Various apparatus embodiments include portable computing devices and cellular telephones.

Abstract: A method of preventing current leakage in logic circuits within level sensitive scan design (LSSD) latch circuits in an application specific integrated circuit (ASIC). When the ASIC is in a manufacturing test mode, a gating signal at an input terminal of a power gating circuit is set to exceed a threshold voltage of transistors within the power gating circuit. The gating signal thus causes the power gating circuit to enable electrical current to reach the LSSD latch circuits. When the ASIC is in a normal functional mode, the gating signal is set below the threshold voltage. The gating signal thus causes the power gating circuit to prevent electrical current from reaching particular logic circuits (e.g., scan logic) within the LSSD latch circuits, thereby conserving power within the ASIC by preventing current leakage and heat generation in the LSSD latch circuit.

Abstract: Methods and apparatuses to decrease power consumption and reduce leakage current of integrated circuits are disclosed. New leakage power saving techniques for various types of integrated circuits, including cache memory circuits, are discussed. Embodiments comprise methods and apparatuses to reduce power consumption in integrated circuits by using virtual voltage rails, or virtual power rails, to supply power to integrated circuit loads. The methods and apparatuses generally involve using one or two virtual power control devices to “head” and “foot”, or sandwich, the integrated circuit loads from firm power supply rails. In these method embodiments, one or more elements sense the voltage of the virtual power rails, or nodes, and make adjustments to control the voltage at certain “virtual” voltage potentials. While controlling the voltage in this manner, the virtual power control devices may serve to restrict unnecessary current flow through the integrated circuit loads.

Abstract: A circuit for a multiplexer includes a pair of NAND gates with outputs coupled to an OAI gate constructed from a complementary circuit formed from solid state devices. A current flow controller formed from solid state devices is coupled to one of the NAND gates. When activated the controller inhibits the flow of current through the NAND gate and a portion of the OAI gate to which the controller is connected. As a consequence, leakage power is not consumed within the multiplexer. Several of the applications in which the circuit is used are also demonstrated in the specification.

Abstract: An eight-transistor tri-state driver. The tri-state driver implements multiple cascade structures where each cascade structure may refer to a pair of complementary transistors serially connected. Each cascade structure may include a p-conductivity type transistor serially connected to a n-conductivity type transistor. By implementing cascade structures in a tri-state driver, there is a lower peak current consumption, a reduced slew rate as well as a reduction in the amount of layout area used in comparison to the classic tri-state drivers.

Abstract: A device is disclosed for providing compensation current continuously to compensate for leakage current at the node of an electrical circuit, such as a chip. The device includes a dummy storage cell, a single staged current mirror circuit and a non reconfigurable keeper circuit. The keeper can be used to compensate for a wide range of leakage corners where the internal storage is located. The adaptive keeper circuit not only increases the robustness of the storage node against leakage caused by process variation but also improves the overall performance of the static storage device connected to the node.

Abstract: A device is disclosed for providing compensation current continuously to compensate for leakage current at the node of an electrical circuit, such as a chip. The device includes a dummy storage cell, a single staged current mirror circuit and a non reconfigurable keeper circuit. The keeper can be used to compensate for a wide range of leakage corners where the internal storage is located. The adaptive keeper circuit not only increases the robustness of the storage node against leakage caused by process variation but also improves the overall performance of the static storage device connected to the node.

Abstract: A device and method for automatically detecting and optimally compensating die leakage current under a wide range of leakage conditions. A variable or reconfigurable (self-adaptive) keeper tracks current leakage online (in real time). The control input to the keeper is coupled to a leakage current sensor, which is in turn coupled to a dummy cell that generates the exact leakage current as the load. The current sensor regulates the control input in real time to produce a leakage compensation enable signal, which reconfigures and/or varies the strength of the keeper. Having the compensation capability of a strong keeper during elevated conditions and the capability of a weaker keeper during normal operational conditions, the self-adaptive keeper system offers high read/write performance, flexibility and circuit robustness in real time.

Abstract: A method and system for automatically detecting and optimally compensating a wide range of die leakage currents in dynamic circuits is presented. A self-adaptive keeper tracks the leakage and reduces the leakage effects by optimally controlled compensation current. The self-adaptive keeper utilizes a 2-stage embedded current mirror circuit, a dummy cell and a keeper transistor to compensate leakage current. The load impact of the self-adaptive keeper on the dynamic circuit components (for example, the impact on memory cells) is minimized by a dummy cell which detects and matches the instant leakage current. Amplification in the 2-stage embedded current mirror circuit provides an optimal current strength in the keeper transistor. The optimally amplified leakage current is utilized to compensate for a leakage induced voltage drop at the circuit's output. Thus, the self-adaptive keeper ensures the robustness of the circuit in real time and does not create any negative trade-off on read latency.

Abstract: A method of preventing current leakage in logic circuits within level sensitive scan design (LSSD) latch circuits in an application specific integrated circuit (ASIC). When the ASIC is in a manufacturing test mode, a gating signal at an input terminal of a power gating circuit is set to exceed a threshold voltage of transistors within the power gating circuit. The gating signal thus causes the power gating circuit to enable electrical current to reach the LSSD latch circuits. When the ASIC is in a normal functional mode, the gating signal is set below the threshold voltage. The gating signal thus causes the power gating circuit to prevent electrical current from reaching particular logic circuits (e.g., scan logic) within the LSSD latch circuits, thereby conserving power within the ASIC by preventing current leakage and heat generation in the LSSD latch circuit.