LEAKAGE DEPENDENT ONLINE PROCESS VARIATION TOLERANT TECHNIQUE FOR INTERNAL STATIC STORAGE NODE
A device is disclosed for providing compensation current continuously to compensate for leakage current at the node of an electrical circuit, such as a chip. The device includes a dummy storage cell, a single staged current mirror circuit and a non reconfigurable keeper circuit. The keeper can be used to compensate for a wide range of leakage corners where the internal storage is located. The adaptive keeper circuit not only increases the robustness of the storage node against leakage caused by process variation but also improves the overall performance of the static storage device connected to the node.
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The present application relates to Application Serial No. (RPS9 20060191US); “Automatic Self-Adaptive Keeper System With Current Sensor For Real-Time /on Line Compensation For Leakage Current Variations”; Filed Jul. 3, 2007; Inventor: Zhibin Cheng and assigned to the assignee of the present invention. The referenced patent application is incorporated in its entirety in the present application.
BACKGROUND OF THE INVENTION1. Technical Field
The present invention generally relates to integrated circuits and in particular to leakage current in integrated circuits. Still more particular, the present invention relates to compensation of leakage current in integrated circuits.
2. Description of Related Art
The use of keeper circuit arrangements to compensate for leakage current at an internal node of a storage device is well known in the prior art. For example, U.S. Pat. Nos. 6,844,750 B2, 7,002,375 B2 U.S. published patent applications U.S. 2004/189337A1 and U.S.2005/01046121 all describe keeper type circuit arrangements. Although, these circuit arrangements work well for intended purposes they share a common set of design characteristics which are not necessarily desirable for some situations or use. The design characteristics are that the keeper circuit arrangements are digitally controlled, over design to compensate for maximum leakage conditions and compensate by varying the physical dimension of the keeper. The physical dimension of the keeper may be varied by increasing/decreasing the number of devices in the keeper circuit.
As a consequence, there is a need to provide a keeper circuit arrangement that do not share the undesirable common design characteristics set forth above, yet still provide compensation on a real time basis for all leakages including leakage resulting from process variation relating to the process use to manufacture the chip.
SUMMARY OF THE INVENTIONDisclosed is a device and method for automatically detecting and optimally compensating for leakage current under a wide range of leakage conditions. The device includes a non-configurable keeper circuit fabricated from a plurality of field effect transistors (FETs) operatively connected in series. The keeper circuit is operatively connected to the node of a storage device to be protected. A current mirror formed by parallel connected FET devices are operatively connected to a leakage current generator which generates leakage current (Ilk1), proportional to the leakage current at the protected node. The leakage current is amplified by the current mirror and supply to the keeper circuit to compensate for the leakage current at the protected node.
The keeper system of the present invention provides online protection that holds the internal storage node (protected node) with optimal compensation strength against leakage. The keeper system also provides on line compensation for leakage resulting from all process variation corners. The keeper system and techniques can also be used as a burn-in keeper. Burn-in tests are done at elevated temperatures and supply voltage conditions which lead to a large increase leakage current in storage circuits such as a wide MUX latch circuit to be described in great detail herein after. This increases the need for utilizing strong keeper to ensure the functionality during the test where weaker keepers can be used in normal operational conditions.
The above as well as additional objective, features and advantages of the present invention will become apparent in the following detailed written description.
The present invention can be used with any node to be protected against leakage current. It works well with a storage system such as a static wide MUX latch circuit. As such it will be described in this environment. However, this should not be construed as in limitation on the scope of the present invention, since it is well within the skill of one skilled in the art to make minor and/or insignificant changes to the embodiment set forth herein. Any such changes are intended to be covered by the claims set forth herein.
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Having described the structure of a circuit that provides analog compensation to the node of a device, its operation will now be given. The leakage current at dummy memory node 108 is sensed and amplified through the current mirror circuit 104. The leakage compensation current is transmitted through a non reconfigurable keeper circuit 102 to internal memory node 110. As a consequence, the adaptive leakage compensation current is generated on line by this circuit while the physical dimension of the keeper circuit remains the same. The current is used to compensate the leakage current Ilk2 (
While the invention has been particularly shown and describe with reference to an embodiment, it should be understood by those skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.
Claims
1. A device for maintaining voltage on a node of a first electrical circuit comprising:
- a leakage current generator for generating a predefined analog current passing through a first transistor of a current mirror circuit;
- a current mirror circuit comprising a first and second transistor, the current mirror circuit coupled to the leakage current generator so that the predefined analog current passes through the first transistor and wherein a second current passes through the second transistor, the second analog current being proportional to the predefined analog current; and
- a non-reconfigurable keeper circuit operatively coupled between and to the second transistor of the current mirror circuit and the node of the first electrical circuit, thereby isolating the current mirror from the node of the first electrical circuit, the keeper circuit comprising a first set of P-type transistors connected in series from drain to source and a second set of N-type transistors connected in series from drain to source to the P-type transistors, thereby exhibiting a node of the keeper circuit between the P-type and N-type transistors, the keeper circuit node being electrically connected to the node of the first electrical circuit, the keeper circuit node further connected through an inverter to all the gates of the N-type and P-type transistors in the keeper circuit.
2. The device of claim 1, wherein the first electrical circuit is a storage device operatively coupled to said node.
3. The device of claim 2, wherein the storage device includes a multiplexer (MUX).
4. The device of claim 2, wherein the predefined analog current is proportional to leakage current caused by said storage device.
5. The device of claim 3, wherein the MUX is in a ratio n:m, wherein n>l and m=1.
6. The device of claim 2, wherein the generator includes a group of dummy bits circuits.
7. The device of claim 6, wherein the group of dummy bits is proportioned to bits in the storage device.
8. The device of claim 1, wherein the current mirror includes a first device for sensing current at a first node and a second device for amplifying sensed current and providing said sensed current at a second node.
9. The device of claim 1, wherein the current mirror includes a single stage.
10-13. (canceled)
Type: Application
Filed: Jul 12, 2007
Publication Date: Jan 15, 2009
Applicant: INTERNATIONAL BUSINESS MACHINES (Armonk, NY)
Inventor: Zhibin Cheng (Cary, NC)
Application Number: 11/776,820
International Classification: H03K 19/02 (20060101);