Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.

Abstract: A non-volatile memory cell includes a bottom electrode, a top electrode having a conductive material, a resistive layer interposed between the bottom electrode and the top electrode, and side portions covering sides of the top electrode and the resistive layer. The side portions contain an oxide of the conductive material. The non-volatile memory cell further includes a contact wire disposed on the top electrode. A width of the contact wire is less than a width between lateral outer surfaces of the side portions.

Abstract: Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.

Abstract: Disclosed is a sub-Kelvin temperature zone refrigeration mechanism. The sub-Kelvin temperature zone refrigeration mechanism includes a pulse tube refrigeration unit, first pre-cooling heat exchangers, a throttling refrigeration unit, second pre-cooling heat exchangers, an adsorption refrigeration unit, a third pre-cooling heat exchanger and a dilution refrigeration unit. The pulse tube refrigeration unit includes a pulse tube refrigeration part. The throttling refrigeration unit includes a throttling refrigeration part, and the throttling refrigeration part is connected with the adsorption refrigeration unit through the second pre-cooling heat exchangers so as to pre-cool the adsorption refrigeration unit. The adsorption refrigeration unit includes an adsorption refrigeration part, and the adsorption refrigeration part is connected with the dilution refrigeration unit through the third pre-cooling heat exchanger.

Abstract: A computer-implemented method for partially supervised image segmentation having improved strong mask generalization includes obtaining, by a computing system including one or more computing devices, a machine-learned segmentation model, the machine-learned segmentation model including an anchor-free detector model and a deep mask head network, the deep mask head network including an encoder-decoder structure having a plurality of layers. The computer-implemented method includes obtaining, by the computing system, input data including tensor data. The computer-implemented method includes providing, by the computing system, the input data as input to the machine-learned segmentation model. The computer-implemented method includes receiving, by the computing system, output data from the machine-learned segmentation model, the output data including a segmentation of the tensor data, the segmentation including one or more instance masks.

Abstract: Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.

Abstract: Circuitry for adjusting luminance of a display device is provided. The circuitry includes a non-volatile memory array having a plurality memory cells configured to store luminance data of the display device, and a luminance adjusting circuit configured to receive image data to be displayed on the display device. The luminance adjusting circuit is coupled directly to the non-volatile memory array to receive the luminance data of the display device from the non-volatile memory array and adjust the image data based on the luminance data of the display device.

Abstract: A method includes receiving video data that includes a series of frames of image data. Here, the video data is representative of an actor performing an activity. The method also includes processing the video data to generate a spatial input stream including a series of spatial images representative of spatial features of the actor performing the activity, a temporal input stream representative of motion of the actor performing the activity, and a pose input stream including a series of images representative of a pose of the actor performing the activity. Using at least one neural network, the method also includes processing the temporal input stream, the spatial input stream, and the pose input stream. The method also includes classifying, by the at least one neural network, the activity based on the temporal input stream, the spatial input stream, and the pose input stream.

Abstract: A computer includes a processor and a memory, and the memory stores instructions executable by the processor to receive a set of points indicating a lane boundary; select a first subset of the points, wherein the set of points includes a first point that is not in the first subset; determine a path of the lane boundary based on the first subset of the points; and, upon determining that the first point is greater than a threshold distance from the path, add the first point to the first subset.

Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

Abstract: A method includes receiving video data that includes a series of frames of image data. Here, the video data is representative of an actor performing an activity. The method also includes processing the video data to generate a spatial input stream including a series of spatial images representative of spatial features of the actor performing the activity, a temporal input stream representative of motion of the actor performing the activity, and a pose input stream including a series of images representative of a pose of the actor performing the activity. Using at least one neural network, the method also includes processing the temporal input stream, the spatial input stream, and the pose input stream. The method also includes classifying, by the at least one neural network, the activity based on the temporal input stream, the spatial input stream, and the pose input stream.

Abstract: Disclosed is a resistive random access memory (RRAM) circuit and related method to limit current, or ramp voltage, applied to a source line or bitline of an RRAM array. The RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.

Abstract: Systems and methods of the present disclosure are directed to a computer-implemented method for training a machine-learned multi-class object classification model with partially labeled training data. The method can include obtaining image data depicting objects and ground truth data comprising a subset of object class annotations respectively associated with a subset of object classes of a plurality of object classes. The method can include processing the image data with the machine-learned multi-class object classification model to obtain object classification data. The method can include evaluating a loss function that evaluates a multi-class classification loss and adjusting one or more parameters of the multi-class object classification model based on the loss function.

Abstract: A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell may be determined to a higher bit resolution than a data read value. A write condition may be selected for the RRAM cell, based on the cell characteristic. The RRAM cell may be written to, using the selected write condition.

Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.

Abstract: A non-volatile memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines extended in a row direction, and a plurality of bit lines extended in a column direction. Each of the memory cells is coupled to one of the word lines and one of the bit lines. The memory device further includes a word-line control circuit coupled to and configured to control the word lines, a first bit-line control circuit configured to control the bit lines and sense the memory cells in a digital mode, and a second bit-line control circuit configured to bias the bit lines and sense the memory cells in an analog mode. The first bit-line control circuit is coupled to a first end of each of the bit lines. The second bit-line control circuit is coupled to a second end of each of the bit lines.

Abstract: A resistive random access memory (RRAM) circuit and related method limits current, or ramp voltage, applied to a source line or bitline of an RRAM array. The RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.

Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.

Abstract: Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.

Abstract: Circuitry for adjusting luminance of a display device is provided. The circuitry includes a non-volatile memory array having a plurality memory cells configured to store luminance data of the display device, and a luminance adjusting circuit configured to receive image data to be displayed on the display device. The luminance adjusting circuit is coupled directly to the non-volatile memory array to receive the luminance data of the display device from the non-volatile memory array and adjust the image data based on the luminance data of the display device.