Patents by Inventor Zhichao Lu

Zhichao Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11132576
    Abstract: A text recognition method, a text recognition apparatus, an electronic device, and a storage medium are provided. The method includes: extracting character prediction regions of a text line image using a constructed text recognition model, to obtain a character region set; calculating horizon-distance IOUs between the character prediction regions in the character region set according to a position of each character prediction region in the character region set; removing overlapped character prediction regions from the character region set, according to the horizon-distance IOUs between the character prediction regions in the character region set, to obtain a character position set; and sorting and outputting character categories corresponding to the character prediction regions in the character position set according to positions of the character prediction regions in the character position set.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: September 28, 2021
    Assignee: AInnovation (Shanghai) Technology Co., Ltd.
    Inventors: Faen Zhang, Qiang Lu, Zhichao Yuan, Tianqi Sun, Hui Xu
  • Publication number: 20210275998
    Abstract: Some embodiments of the invention include inventive catalysts (e.g., catalysts of Formula (I)). Other embodiments include compositions comprising the inventive catalysts. Some embodiments include methods of using the inventive catalysts (e.g., in hydrofluorination of an organic compound). Further embodiments include methods for making the inventive catalysts. Additional embodiments of the invention are also discussed herein.
    Type: Application
    Filed: July 22, 2019
    Publication date: September 9, 2021
    Applicant: UNIVERSITY OF LOUISVILLE RESEARCH FOUNDATION, INC.
    Inventors: Bo XU, Zhichao LU, Gerald B. HAMMOND
  • Publication number: 20210264189
    Abstract: A text recognition method, a text recognition apparatus, an electronic device, and a storage medium are provided. The method includes: extracting character prediction regions of a text line image using a constructed text recognition model, to obtain a character region set; calculating horizon-distance IOUs between the character prediction regions in the character region set according to a position of each character prediction region in the character region set; removing overlapped character prediction regions from the character region set, according to the horizon-distance IOUs between the character prediction regions in the character region set, to obtain a character position set; and sorting and outputting character categories corresponding to the character prediction regions in the character position set according to positions of the character prediction regions in the character position set.
    Type: Application
    Filed: June 15, 2020
    Publication date: August 26, 2021
    Applicant: AInnovation (Shanghai) Technology Co., Ltd.
    Inventors: Faen Zhang, Qiang Lu, Zhichao Yuan, Tianqi Sun, Hui Xu
  • Publication number: 20210257014
    Abstract: Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.
    Type: Application
    Filed: May 5, 2021
    Publication date: August 19, 2021
    Inventors: Zhichao LU, Liang ZHAO
  • Patent number: 11081168
    Abstract: A non-volatile memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines extended in a row direction, and a plurality of bit lines extended in a column direction. Each of the memory cells is coupled to one of the word lines and one of the bit lines. The memory device further includes a word-line control circuit coupled to and configured to control the word lines, a first bit-line control circuit configured to control the bit lines and sense the memory cells in a digital mode, and a second bit-line control circuit configured to bias the bit lines and sense the memory cells in an analog mode. The first bit-line control circuit is coupled to a first end of each of the bit lines. The second bit-line control circuit is coupled to a second end of each of the bit lines.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: August 3, 2021
    Assignee: Hefei Reliance Memory Limited
    Inventors: Liang Zhao, Zhichao Lu
  • Publication number: 20210234093
    Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.
    Type: Application
    Filed: April 14, 2021
    Publication date: July 29, 2021
    Inventors: Zhichao LU, Gary Bela BRONNER
  • Patent number: 11069391
    Abstract: Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.
    Type: Grant
    Filed: November 24, 2019
    Date of Patent: July 20, 2021
    Assignee: Hefei Reliance Memory Limited
    Inventors: Zhichao Lu, Liang Zhao
  • Patent number: 11018295
    Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: May 25, 2021
    Assignee: Hefei Reliance Memory Limited
    Inventors: Zhichao Lu, Gary Bela Bronner
  • Patent number: 10998044
    Abstract: An RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: May 4, 2021
    Assignee: Hefei Reliance Memory Limited
    Inventors: Brent Haukness, Zhichao Lu
  • Publication number: 20210110870
    Abstract: The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.
    Type: Application
    Filed: December 21, 2020
    Publication date: April 15, 2021
    Inventors: Zhichao LU, Brent HAUKNESS, Gary BRONNER
  • Patent number: 10943655
    Abstract: The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: March 9, 2021
    Assignee: Hefei Reliance Memory Limited
    Inventors: Zhichao Lu, Brent Haukness, Gary Bronner
  • Publication number: 20210043256
    Abstract: A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell may be determined to a higher bit resolution than a data read value. A write condition may be selected for the RRAM cell, based on the cell characteristic. The RRAM cell may be written to, using the selected write condition.
    Type: Application
    Filed: October 27, 2020
    Publication date: February 11, 2021
    Inventors: Brent HAUKNESS, Zhichao LU
  • Publication number: 20210035623
    Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 4, 2021
    Inventors: Frederick A. Ware, John Eric Linstadt, Zhichao Lu, Kenneth Lee Wright
  • Publication number: 20210012838
    Abstract: Disclosed is a resistive random access memory (RRAM) circuit and related method to limit current, or ramp voltage, applied to a source line or bitline of an RRAM array. The RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRA.M cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximmn voltage value during a second interval, and ceased after the second time interval.
    Type: Application
    Filed: August 3, 2020
    Publication date: January 14, 2021
    Inventors: Brent HAUKNESS, Zhichao LU
  • Publication number: 20200395539
    Abstract: A non-volatile memory cell includes a bottom electrode, a top electrode having a conductive material, a resistive layer interposed between the bottom electrode and the top electrode, and side portions covering sides of the top electrode and the resistive layer. The side portions contain an oxide of the conductive material. The non-volatile memory cell further includes a contact wire disposed on the top electrode. A width of the contact wire is less than a width between lateral outer surfaces of the side portions.
    Type: Application
    Filed: October 30, 2019
    Publication date: December 17, 2020
    Inventors: Zhiqiang WEI, Zhichao LU
  • Patent number: 10861544
    Abstract: A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell is determined to a finer resolution than a data read value. A write condition is selected for the RRAM cell, based on the cell characteristic. The RRAM cell is written to, using the selected write condition.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: December 8, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Brent Haukness, Zhichao Lu
  • Publication number: 20200381479
    Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Inventors: Zhichao LU, Brent Steven HAUKNESS
  • Publication number: 20200372949
    Abstract: A non-volatile memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines extended in a row direction, and a plurality of bit lines extended in a column direction. Each of the memory cells is coupled to one of the word lines and one of the bit lines. The memory device further includes a word-line control circuit coupled to and configured to control the word lines, a first bit-line control circuit configured to control the bit lines and sense the memory cells in a digital mode, and a second bit-line control circuit configured to bias the bit lines and sense the memory cells in an analog mode. The first bit-line control circuit is coupled to a first end of each of the bit lines. The second bit-line control circuit is coupled to a second end of each of the bit lines.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 26, 2020
    Inventors: Liang ZHAO, Zhichao LU
  • Publication number: 20200327865
    Abstract: Circuitry for adjusting luminance of a display device is provided. The circuitry includes a non-volatile memory array having a plurality memory cells configured to store luminance data of the display device, and a luminance adjusting circuit configured to receive image data to be displayed on the display device. The luminance adjusting circuit is coupled directly to the non-volatile memory array to receive the luminance data of the display device from the non-volatile memory array and adjust the image data based on the luminance data of the display device.
    Type: Application
    Filed: April 7, 2020
    Publication date: October 15, 2020
    Inventors: Liang ZHAO, Zhichao LU, Zhigang HAN
  • Patent number: 10777608
    Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: September 15, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Zhichao Lu, Brent Steven Haukness