Abstract: Some embodiments of the invention include inventive catalysts (e.g., compounds of Formula (I) or (Ia)). Other embodiments include compositions comprising the inventive catalysts. Some embodiments include methods of using the inventive catalysts (e.g., in hydrofluorination of an organic compound). Further embodiments include methods for making the inventive catalysts. Additional embodiments of the invention are also discussed herein.

Abstract: Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.

Abstract: A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell is determined to a finer resolution than a data read value. A write condition is selected for the RRAM cell, based on the cell characteristic. The RRAM cell is written to, using the selected write condition.

Abstract: The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.

Abstract: Disclosed is a resistive random access memory (RRAM) circuit and related method to limit current, or ramp voltage, applied to a source line or bitline of an RRAM array. The RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.

Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.

Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.

Abstract: Some embodiments of the invention include inventive catalysts (e.g., compounds of Formula (I) or (Ia)). Other embodiments include compositions comprising the inventive catalysts. Some embodiments include methods of using the inventive catalysts (e.g., in hydrofluorination of an organic compound). Further embodiments include methods for making the inventive catalysts. Additional embodiments of the invention are also discussed herein.

Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

Abstract: Memory cell structures and biasing schemes are provided. Certain embodiments pertain to a modified floating-body gate cell, which can provide improved retention times. In one embodiment, a gated diode is used to drive the gate of a second transistor structure of a cell. In another embodiment, a body-tied-source (BTS) field effect transistor is used to drive the gate of the second transistor structure of a cell.

Abstract: Multi-gate metal-oxide-semiconductor (MOS) transistors and methods of operating such multi-gate MOS transistors are disclosed. In one embodiment, the multi-gate MOS transistor comprises a first gate associated with a first body factor and comprising a first gate electrode for applying a first gate voltage, and a second gate associated with a second body factor greater than or equal to the first body factor and comprising a second gate electrode for applying a second gate voltage. The multi-gate MOS transistor further comprises a body of semiconductor material between the first dielectric layer and the second dielectric layer, where the semiconductor body comprises a first channel region located close to the first dielectric layer and a second channel region located close to the second dielectric layer. The multi-gate MOS transistor still further comprises a source region and a drain region each having a conductivity type different from a conductivity type of the body.

Abstract: Multi-gate metal-oxide-semiconductor (MOS) transistors and methods of operating such multi-gate MOS transistors are disclosed. In one embodiment, the multi-gate MOS transistor comprises a first gate associated with a first body factor and comprising a first gate electrode for applying a first gate voltage, and a second gate associated with a second body factor greater than or equal to the first body factor and comprising a second gate electrode for applying a second gate voltage. The multi-gate MOS transistor further comprises a body of semiconductor material between the first dielectric layer and the second dielectric layer, where the semiconductor body comprises a first channel region located close to the first dielectric layer and a second channel region located close to the second dielectric layer. The multi-gate MOS transistor still further comprises a source region and a drain region each having a conductivity type different from a conductivity type of the body.

Abstract: The present invention provides a compound powder for making magnetic powder cores, a kind of magnetic powder core, and a process for making them. Said compound powder is a mixture composing of powder A and powder B, the content of powder A is 50-96 wt % and the content of powder B is 4-50 wt %, wherein powder A is at least one selected from iron powder, Fe—Si powder, Fe—Si—Al powder, Fe-based nanocrystalline powder, Fe-based amorphous powder, Fe—Ni powder and Fe—Ni—Mo powder; powder B bears different requirement characteristics from powder A and is at least one selected from iron powder, Fe—Si powder, Fe—Si—Al powder, Fe-based nanocrystalline powder, Fe-based amorphous powder, Fe—Ni powder and Fe—Ni—Mo powder. Said powder B adopts Fe-based amorphous soft magnetic powder with good insulation property as insulating agent and thus core loss of magnetic powder core decreases.

Abstract: Memory cell structures and biasing schemes are provided. Certain embodiments pertain to a modified floating-body gate cell, which can provide improved retention times. In one embodiment, a gated diode is used to drive the gate of a second transistor structure of a cell. In another embodiment, a body-tied-source (BTS) field effect transistor is used to drive the gate of the second transistor structure of a cell.

Abstract: The present invention provides a compound powder for making magnetic powder cores, a kind of magnetic powder core, and a process for making them. Said compound powder is a mixture composing of powder A and powder B, the content of powder A is 50-96 wt. % and the content of powder B is 4-50 wt. %, wherein powder A is at least one selected from iron powder, Fe—Si powder, Fe—Si—Al powder, Fe-based nanocrystalline powder, Fe-based amorphous powder, Fe—Ni powder and Fe—Ni—Mo powder; powder B bears different requirement characteristics from powder A and is at least one selected from iron powder, Fe—Si powder, Fe—Si—Al powder, Fe-based nanocrystalline powder, Fe-based amorphous powder, Fe—Ni powder and Fe—Ni—Mo powder. Said powder B adopts Fe-based amorphous soft magnetic powder with good insulation property as insulating agent and thus core loss of magnetic powder core decreases.

Abstract: The present invention provides a compound powder for making magnetic powder cores, a kind of magnetic powder core, and a process for making them. Said compound powder is a mixture composing of powder A and powder B, the content of powder A is 50-96 wt. % and the content of powder B is 4-50 wt. %, wherein powder A is at least one selected from iron powder, Fe—Si powder, Fe—Si—Al powder, Fe-based nanocrystalline powder, Fe-based amorphous powder, Fe—Ni powder and Fe—Ni—Mo powder; powder B bears different requirement characteristics from powder A and is at least one selected from iron powder, Fe—Si powder, Fe—Si—Al powder, Fe-based nanocrystalline powder, Fe-based amorphous powder, Fe—Ni powder and Fe—Ni—Mo powder. Said powder B adopts Fe-based amorphous soft magnetic powder with good insulation property as insulating agent and thus core loss of magnetic powder core decreases.

Abstract: The present invention provides an amorphous alloy powder and magnetic powder cores exhibiting excellent high frequency properties and a method for making themof. The composition of said alloy powder by atomic percentage satisfies the following formula: (Fe1-xMx)100-a-b-cPaTbDc, wherein M represents at least one element of Co and Ni; T is over three elements selected from Al, C, B and Si, D is at least one element of Sn, Cr, Mn, Mo, W, V, Nb, Ta, Ti, Zr, Hf, Pt, Pd and Au; the subscripts x, a, b, and c satisfy the relationships 0.01?x?0.16, 8?a?15, 10?b?25 and 0.5?c?6. The said amorphous alloy powder is made by atomization method and a magnetic powder core comprises a molded article of mixture of the said alloy powder and an insulating material. A method of making the amorphous alloy powder core includes the steps of screening, insulating, compacting, annealing and spray painting.

Abstract: The present invention provides an amorphous alloy powder and magnetic powder cores exhibiting excellent high frequency properties and a method for making themof. The composition of said alloy powder by atomic percentage satisfies the following formula: (Fe1-xMx)100-a-b-cPaTbDc, wherein M represents at least one element of Co and Ni; T is over three elements selected from Al, C, B and Si, D is at least one element of Sn, Cr, Mn, Mo, W, V, Nb, Ta, Ti, Zr, Hf, Pt, Pd and Au; the subscripts x, a, b, and c satisfy the relationships 0.01?x?0.16, 8?a?15, 10?b?25 and 0.5?c?6. The said amorphous alloy powder is made by atomization method and a magnetic powder core comprises a molded article of mixture of the said alloy powder and an insulating material. A method of making the amorphous alloy powder core includes the steps of screening, insulating, compacting, annealing and spray painting.

Abstract: The present invention provides an amorphous alloy powder and magnetic powder cores exhibiting excellent high frequency properties and a method for making themof The composition of said alloy powder by atomic percentage satisfies the following formula: (Fe1-xMx)100-a-b-cPaTbDc, wherein M represents at least one element of Co and Ni; T is over three elements selected from Al, C, B and Si, D is at least one element of Sn, Cr, Mn, Mo, W, V, Nb, Ta, Ti, Zr, Hf, Pt, Pd and Au; the subscripts x, a, b, and c satisfy the relationships 0.01?x?0.16, 8?a?15, 10?b?25 and 0.5?c?6. The said amorphous alloy powder is made by atomization method and a magnetic powder core comprises a molded article of mixture of the said alloy powder and an insulating material. A method of making the amorphous alloy powder core includes the steps of screening, insulating, compacting, annealing and spray painting.

Abstract: The present invention provides a compound powder for making magnetic powder cores, a kind of magnetic powder core, and a process for making them. Said compound powder is a mixture composing of powder A and powder B, the content of powder A is 50-96 wt % and the content of powder B is 4-50 wt %, wherein powder A is at least one selected from iron powder, Fe—Si powder, Fe—Si—Al powder, Fe-based nanocrystalline powder, Fe-based amorphous powder, Fe—Ni powder and Fe—Ni—Mo powder; powder B bears different requirement characteristics from powder A and is at least one selected from iron powder, Fe—Si powder, Fe—Si—Al powder, Fe-based nanocrystalline powder, Fe-based amorphous powder, Fe—Ni powder and Fe—Ni—Mo powder. Said powder B adopts Fe-based amorphous soft magnetic powder with good insulation property as insulating agent and thus core loss of magnetic powder core decreases.