Patents by Inventor Zhicheng DING
Zhicheng DING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11894344Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.Type: GrantFiled: April 6, 2022Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Zhijun Xu, Bin Liu, Yong She, Zhicheng Ding
-
Patent number: 11848281Abstract: A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.Type: GrantFiled: August 2, 2021Date of Patent: December 19, 2023Assignee: Intel CorporationInventors: Yong She, Bin Liu, Zhicheng Ding, Aiping Tan
-
Patent number: 11830848Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include an electronic component, a redistribution layer, and an interposer electrically coupling the redistribution layer and the electronic component. The interposer can have interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer. A density of the interconnect interfaces on the top side can be greater than a density of the interconnect interfaces on the bottom side. Associated systems and methods are also disclosed.Type: GrantFiled: December 31, 2016Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Zhicheng Ding, Bin Liu, Yong She, Hyoung Il Kim
-
Patent number: 11742284Abstract: Embodiments described herein provide techniques of forming an interconnect structure using lithographic and deposition processes. The interconnect structure can be used to couple components of a semiconductor package. For one example, a semiconductor package includes a die stack and an interconnect structure formed on the die stack. The die stack comprises a plurality of dies. Each die in the die stack comprises: a first surface; a second surface opposite the first surface; sidewall surfaces coupling the first surface to the second surface; and a pad on the first surface. A one sidewall surface of one of the dies has a sloped profile. The semiconductor package also includes an interconnect structure positioned on the first surfaces and the sidewall with the sloped profile. In this semiconductor package, the interconnect structure electrically couples the pad on each of the dies to each other.Type: GrantFiled: December 12, 2018Date of Patent: August 29, 2023Assignee: Intel CorporationInventors: Zhicheng Ding, Bin Liu, Yong She, Zhijun Xu
-
Patent number: 11538746Abstract: A system in package includes a memory-die stack in memory module that is stacked vertically with respect to a processor die. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. Some configurations include the vertical bond wire emerging orthogonally beginning from a bond-wire pad. The matrix encloses the memory-die stack, the spacer, and at least a portion of the processor die.Type: GrantFiled: December 23, 2016Date of Patent: December 27, 2022Assignee: Intel CorporationInventors: Zhicheng Ding, Yong She, Bin Liu, Aiping Tan, Li Deng
-
Publication number: 20220230995Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.Type: ApplicationFiled: April 6, 2022Publication date: July 21, 2022Applicant: INTEL CORPORATIONInventors: Zhijun Xu, Bin Liu, Yong She, Zhicheng Ding
-
Patent number: 11302671Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.Type: GrantFiled: September 29, 2017Date of Patent: April 12, 2022Assignee: Intel CorporationInventors: Zhijun Xu, Bin Liu, Yong She, Zhicheng Ding
-
Publication number: 20220093568Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a plurality of cavities, and a plurality of adhesives in the cavities of the package substrate. The semiconductor package also includes a plurality of stacked dies over the adhesives and the package substrate, where the stacked dies are coupled to the adhesives with spacers. The spacers may be positioned below outer edges of the stacked dies. The adhesives may include a plurality of films. The semiconductor package may further include a plurality of interconnects coupled to the stacked dies and package substrate, a plurality of electrical components on the package substrate, a mold layer over the stacked dies, interconnects, spacers, adhesives, and electrical components, and a plurality of adhesive layers coupled to the plurality of stacked dies, where one of the adhesive layers couples the stacked dies to the spacers.Type: ApplicationFiled: February 22, 2019Publication date: March 24, 2022Inventors: Jianfeng HU, Zhicheng DING, Yong SHE, Zhijun XU
-
Publication number: 20220020704Abstract: A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.Type: ApplicationFiled: August 2, 2021Publication date: January 20, 2022Inventors: Yong She, Bin Liu, Zhicheng Ding, Aiping Tan
-
Patent number: 11148044Abstract: The present disclosure provides an input device for an intelligent terminal, wherein the input device is in communication connection with the intelligent terminal and transmits a received input operation to the intelligent terminal, the input operation is displayed on a screen of the intelligent terminal, and the input device includes at least one operating portion; one end of the input device is recessed inwardly to form a recess, and the recess accommodates a top portion or a bottom portion of the intelligent terminal; when the input device is connected with the intelligent terminal, the top portion or the bottom portion of the intelligent terminal is inserted into the recess, the operating portion and the screen of the intelligent terminal are arranged on a same side, and a display interface of the screen of the intelligent terminal is exposed in a projection range of the operating portion.Type: GrantFiled: October 24, 2018Date of Patent: October 19, 2021Assignee: SHANGHAI ZHONGLIAN TECHNOLOGIES LTD., COInventors: Haitao Duan, Zhicheng Ding, Peng Li
-
Publication number: 20210265305Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include an electronic component, a redistribution layer, and an interposer electrically coupling the redistribution layer and the electronic component. The interposer can have interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer. A density of the interconnect interfaces on the top side can be greater than a density of the interconnect interfaces on the bottom side. Associated systems and methods are also disclosed.Type: ApplicationFiled: December 31, 2016Publication date: August 26, 2021Applicant: Intel CorporationInventors: Zhicheng Ding, Bin Liu, Yong She, Hyoung Il Kim
-
Patent number: 11101254Abstract: A system in package and method for making a system in package. A plurality of passive devices are coupled to an interposer. A molding compound envelopes the plurality of passive devices and defines a platform having a substantially planar surface. The interposer is coupled to a substrate. A plurality of integrated circuit dies are coupled in a stack to the planar surface.Type: GrantFiled: December 25, 2015Date of Patent: August 24, 2021Assignee: Intel CorporationInventors: Zhicheng Ding, Bin Liu
-
Patent number: 11081451Abstract: A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.Type: GrantFiled: March 10, 2017Date of Patent: August 3, 2021Assignee: Intel CorporationInventors: Yong She, Bin Liu, Zhicheng Ding, Aiping Tan
-
Patent number: 10991679Abstract: A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.Type: GrantFiled: September 3, 2020Date of Patent: April 27, 2021Assignee: Intel CorporationInventors: Zhicheng Ding, Bin Liu, Yong She, Aiping Tan, Li Deng
-
Publication number: 20210057326Abstract: Embodiments described herein provide techniques of forming an interconnect structure using lithographic and deposition processes. The interconnect structure can be used to couple components of a semiconductor package. For one example, a semiconductor package includes a die stack and an interconnect structure formed on the die stack. The die stack comprises a plurality of dies. Each die in the die stack comprises: a first surface; a second surface opposite the first surface; sidewall surfaces coupling the first surface to the second surface; and a pad on the first surface. A one sidewall surface of one of the dies has a sloped profile. The semiconductor package also includes an interconnect structure positioned on the first surfaces and the sidewall with the sloped profile. In this semiconductor package, the interconnect structure electrically couples the pad on each of the dies to each other.Type: ApplicationFiled: December 12, 2018Publication date: February 25, 2021Applicant: Intel CorporationInventors: Zhicheng DING, Bin LIU, Yong SHE, Zhijun XU
-
Patent number: 10930622Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.Type: GrantFiled: July 27, 2020Date of Patent: February 23, 2021Assignee: Intel CorporationInventors: Zhicheng Ding, Bin Liu, Yong She, Aiping Tan, Li Deng
-
Patent number: 10910347Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.Type: GrantFiled: July 19, 2019Date of Patent: February 2, 2021Assignee: Intel CorporationInventors: Yong She, John G. Meyers, Zhicheng Ding, Richard Patten
-
Publication number: 20200402961Abstract: A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.Type: ApplicationFiled: September 3, 2020Publication date: December 24, 2020Inventors: Zhicheng Ding, Bin Liu, Yong She, Aiping Tan, Li Deng
-
Publication number: 20200357773Abstract: A pre-packaged stair-stacked memory module is mounted on a board with at least one additional component. A stair-stacked memory module includes a plurality of memory dice that are stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die. The matrix might also enclose the at least one additional component.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Zhicheng Ding, Bin Liu, Yong She, Aiping Tan, Li Deng
-
Publication number: 20200316460Abstract: The present disclosure provides an input device for an intelligent terminal, wherein the input device is in communication connection with the intelligent terminal and transmits a received input operation to the intelligent terminal, the input operation is displayed on a screen of the intelligent terminal, and the input device includes at least one operating portion; one end of the input device is recessed inwardly to form a recess, and the recess accommodates a top portion or a bottom portion of the intelligent terminal; when the input device is connected with the intelligent terminal, the top portion or the bottom portion of the intelligent terminal is inserted into the recess, the operating portion and the screen of the intelligent terminal are arranged on a same side, and a display interface of the screen of the intelligent terminal is exposed in a projection range of the operating portion.Type: ApplicationFiled: October 24, 2018Publication date: October 8, 2020Inventors: Haitao DUAN, Zhicheng DING, Peng LI